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Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

onsemi MC10113FN

Name: MC10113FN
Brand: onsemi
SKU: MC10113FN
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: MC10113FN

Manufacturer:: onsemi

Category:: Gates and Inverters

Package:: -

Datasheet:: MC10113FN.pdf

Description:: IC GATE XOR 2-INP

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Product details

Overview

MC10113FN from ON Semiconductor is a quad ECL-exclusive OR gate with common active-low enable, designed for high-speed digital comparison and arithmetic logic in MECL 10,000-series systems. It delivers 2.5 ns typical propagation delay, 2.0 ns typical rise/fall time (20–80%), and operates across –30°C to +85°C with –5.2 V VEE supply. Used in 4-bit equality comparators where wire-OR outputs implement A = B logic.

For engineers reviewing the MC10113FN datasheet, pinout, applications, or equivalent options, this page provides verified package mapping (PLCC-20), terminal-level truth table behavior, ECL-specific voltage thresholds (VOH = –0.810 V typ, VOL = –1.850 V typ), and direct substitution guidance against industry-standard MECL XOR alternatives.

Technical Context

The MC10113FN implements four independent ECL XOR gates sharing a single active-low enable input (Pin 9), enabling synchronous gating of all outputs. Its differential ECL interface requires –5.2 V VEE (Pin 8), +1.11 V reference (applied to inputs), and termination to –2.0 V via 50 Ω loads - critical for maintaining signal integrity at >300 MHz toggle rates.

All gates meet MECL 10,000 DC specifications after thermal equilibrium, with VOHA = –0.980 V and VOLA = –1.630 V at +25°C, defining valid logic 1/0 switching thresholds. Outputs are current-mode logic compatible and support wired-OR connection without external pull-ups, directly enabling 4-bit magnitude comparison functionality.

Key Specifications

Parameter	Value and Actual Design Meaning
Propagation Delay	2.5 ns typical (t_pd), measured under 50 Ω load; enables sub-400 MHz clock domain operation in comparator chains.
Rise/Fall Time	2.0 ns typical (20–80%), ensuring clean edge transitions for high-fidelity timing in pipelined logic.
Supply Voltage	V_EE = –5.2 V; fixed negative rail required for ECL biasing - no positive V_CC needed beyond reference levels.
Output Logic Levels	V_OH = –0.810 V, V_OL = –1.850 V (typ @ +25°C); defines noise margin of ~1.04 V for robust inter-gate signaling.
Enable Polarity	Active-low (E = L enables all gates); simplifies system-level control with open-collector or TTL-compatible drivers.
Operating Temperature	–30°C to +85°C; validated across industrial temperature range with full DC parameter compliance.
Power Dissipation	175 mW typical per package (no load); consistent with MECL 10,000 family thermal design rules.

Pinout & Package

MC10113FN uses a 20-pin Plastic Leaded Chip Carrier (PLCC-20), Case 775–02, with J-lead profile and seating plane defined per ANSI Y14.5M. Dimensions: 10.03 mm × 10.03 mm body, 0.81 mm max height, 0.64 mm lead pitch.

Pin/Terminal	Circuit Role	Design Meaning
1, 16	V_CC Reference	Not power rails - used as reference return points for internal bias networks; tied to system ground or –2.0 V termination point.
2, 3, 14, 15	Outputs (AOUT, BOUT, COUT, DOUT)	Emitter-follower outputs supporting wired-OR; drive 50 Ω to –2.0 V for standard MECL interfacing.
4, 5, 6, 7, 10, 11, 12, 13	Inputs (AIN, BIN, CIN, DIN ×2 each)	Differential pair inputs; require VIH = –0.810 V, VIL = –1.850 V (typ) for valid logic states.
8	V_EE	Main negative supply (–5.2 V); common to all gates and critical for ECL bias stability.
9	ENABLE (E)	Active-low global enable; when low, all four XOR gates operate; when high, all outputs go high-impedance (logic 1 state).

Key Features

Feature	Design Value
Quad XOR with shared enable	Reduces component count in multi-bit comparator designs - one MC10113FN replaces four discrete XORs plus external gating logic.
Wired-OR output capability	Enables direct implementation of 4-bit equality detection (A = B) without external diodes or resistors - outputs shorted to single node yield AND-of-XORs.
MECL 10,000–compliant timing	Guaranteed t_pd ≤ 5.0 ns max across temperature ensures compatibility with legacy ECL systems using MC10100-series timing budgets.
Industrial temperature support	Full parameter validation from –30°C to +85°C allows deployment in base station timing, test equipment, and avionics subsystems.
ECL-specific threshold margins	V_OHA = –0.980 V and V_OLA = –1.630 V (typ @ +25°C) provide 0.65 V noise immunity - essential for reliable operation in noisy RF-adjacent environments.

Applications

High-Speed Digital Comparator	Phase Detection Circuit
Use Scenario: Real-time comparison of two 4-bit parallel data words in a digital signal processor's ALU pipeline. IC Role / Device Role / Timing Role: Performs bitwise XOR on corresponding bits, with ENABLE synchronized to clock edge; wired-OR output yields single A = B flag. Use Value: Delivers deterministic 2.5 ns latency per bit comparison, enabling sub-cycle equality checks without pipeline stalls.	Use Scenario: Detecting zero-crossing alignment between two high-frequency clock signals in a PLL feedback path. IC Role / Device Role / Timing Role: Compares phase-aligned quadrature signals (I/Q) to generate error pulses; ENABLE disables detection during lock acquisition. Use Value: 2.0 ns edge fidelity preserves sub-nanosecond timing resolution required for <10 ps phase error detection.
Bitwise Arithmetic Logic Unit	ECL-Based Test Equipment Interface
Use Scenario: Building carry-lookahead adder stages in a radiation-hardened flight computer using MECL logic families. IC Role / Device Role / Timing Role: Implements sum generation (A ⊕ B ⊕ C_in) across four bits; ENABLE isolates logic during reset sequences. Use Value: Matches propagation delay of MC10102 and MC10107 components, ensuring timing closure in mixed MECL-10K datapaths.	Use Scenario: Signal conditioning stage in automated test equipment generating precise strobe windows for memory read/write verification. IC Role / Device Role / Timing Role: Compares expected vs. captured data patterns; ENABLE gated by pattern generator sequencer. Use Value: 175 mW typical dissipation enables dense PLCC-20 placement on high-channel-count ATE backplanes without thermal derating.

High-Speed Digital Comparator

Phase Detection Circuit

Use Scenario: Real-time comparison of two 4-bit parallel data words in a digital signal processor's ALU pipeline.

IC Role / Device Role / Timing Role: Performs bitwise XOR on corresponding bits, with ENABLE synchronized to clock edge; wired-OR output yields single A = B flag.

Use Value: Delivers deterministic 2.5 ns latency per bit comparison, enabling sub-cycle equality checks without pipeline stalls.

Use Scenario: Detecting zero-crossing alignment between two high-frequency clock signals in a PLL feedback path.

IC Role / Device Role / Timing Role: Compares phase-aligned quadrature signals (I/Q) to generate error pulses; ENABLE disables detection during lock acquisition.

Use Value: 2.0 ns edge fidelity preserves sub-nanosecond timing resolution required for <10 ps phase error detection.

Bitwise Arithmetic Logic Unit

ECL-Based Test Equipment Interface

Use Scenario: Building carry-lookahead adder stages in a radiation-hardened flight computer using MECL logic families.

IC Role / Device Role / Timing Role: Implements sum generation (A ⊕ B ⊕ C_in) across four bits; ENABLE isolates logic during reset sequences.

Use Value: Matches propagation delay of MC10102 and MC10107 components, ensuring timing closure in mixed MECL-10K datapaths.

Use Scenario: Signal conditioning stage in automated test equipment generating precise strobe windows for memory read/write verification.

IC Role / Device Role / Timing Role: Compares expected vs. captured data patterns; ENABLE gated by pattern generator sequencer.

Use Value: 175 mW typical dissipation enables dense PLCC-20 placement on high-channel-count ATE backplanes without thermal derating.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad XOR gate applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MC10113P	Same logic function and timing, but in PDIP-16 package; lacks PLCC mechanical compatibility and thermal performance.	Preferred for prototyping or through-hole PCBs; unsuitable for surface-mount high-density layouts requiring PLCC footprint.	Select MC10113P only when manual assembly or socket-based testing is required - not for production SMT lines.
SN54LS86J	TTL-family quad XOR (74LS86 variant); 15 ns t_pd, +5 V supply, incompatible voltage levels and termination scheme.	Used in legacy TTL systems; cannot interoperate with ECL buses or replace MC10113FN without level-shifting and redesign.	Choose SN54LS86J only in pure TTL environments - no drop-in replacement; requires full schematic and layout revision.

Compared with MC10113P and SN54LS86J, the MC10113FN uniquely supports high-speed ECL systems via its PLCC-20 package, –5.2 V VEE operation, and 2.5 ns propagation delay - making it irreplaceable in MECL 10,000 timing-critical comparator and arithmetic functions.

Availability

MC10113FN is available at Aetrix Electronics and suitable for high-speed digital comparators, phase detection circuits, ECL-based test equipment interfaces, and bitwise arithmetic logic units requiring stable component supply across extended temperature ranges.

Supply support for MC10113FN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

ON Semiconductor (formerly part of Motorola Semiconductor) is a global supplier of high-performance silicon solutions for automotive, industrial, cloud power, and sensing applications.

The MC10113FN belongs to the MECL 10,000 logic family - engineered specifically for ultra-high-speed digital systems demanding sub-5 ns propagation delays and ECL-compatible noise immunity in mission-critical infrastructure.

FAQ

What is the correct termination configuration for MC10113FN outputs?

The MC10113FN outputs must be terminated to –2.0 V through 50 Ω resistors to maintain signal integrity and meet specified switching times. This termination is mandatory per the datasheet's test conditions and ensures VOH/VOL levels remain within –0.810 V and –1.850 V (typ). Failure to use –2.0 V termination will degrade t_pd and increase jitter in the MC10113FN output waveform.

Does MC10113FN support wired-OR logic, and how is it implemented?

Yes, the MC10113FN supports wired-OR logic: its emitter-follower outputs can be directly connected together without damage. When multiple outputs are shorted, the resulting node assumes the logical AND of individual XOR results - enabling compact 4-bit equality detection (A = B) without external gates. This behavior is explicitly validated in the logic diagram and truth table of the MC10113FN datasheet.

What is the function of Pins 1 and 16 on the MC10113FN PLCC-20 package?

Pins 1 and 16 on the MC10113FN are V_CC reference terminals - not power supply pins. They serve as bias reference returns for internal ECL circuitry and must be connected to the system's –2.0 V termination rail or ground, depending on board-level termination strategy. These pins do not source or sink significant current and are not interchangeable with V_EE (Pin 8) in the MC10113FN.

Can MC10113FN operate with a +5 V supply instead of –5.2 V VEE?

No, the MC10113FN requires –5.2 V applied to Pin 8 (VEE) to bias its ECL transistors correctly. A +5 V supply is incompatible and will prevent proper logic operation or cause permanent damage. The MC10113FN has no positive V_CC pin; its operation depends entirely on the negative rail and referenced input voltages (VIH/VIL), as defined in the MC10113FN electrical characteristics table.

How does the ENABLE pin (Pin 9) affect MC10113FN output states?

The ENABLE pin (Pin 9) on the MC10113FN is active-low: when pulled low, all four XOR gates operate normally; when high, all outputs enter a high-impedance state biased toward logic 1 (–0.810 V). This allows dynamic gating of comparator outputs without external tri-state buffers - a key feature confirmed in the MC10113FN truth table and logic diagram.

MC10113FN Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: *

Package/Case:: -

Packaging:: Bulk

Product Status:: Active

Logic Type:: -

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Number of Inputs:: -

Features:: -

Voltage - Supply:: -

Current - Quiescent (Max):: -

Current - Output High, Low:: -

Input Logic Level - Low:: -

Input Logic Level - High:: -

Max Propagation Delay @ V, Max CL:: -

Operating Temperature:: -

Grade:: -

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MC10113FN FAQ

1.How can I place an order for MC10113FN through Aetrix?

Please submit a Request for Quotation (RFQ) for MC10113FN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MC10113FN reliable?

The price and inventory of MC10113FN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC10113FN is usually 5 days.

3.What payment methods are accepted for MC10113FN?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC10113FN transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MC10113FN?

MC10113FN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MC10113FN order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MC10113FN?

For technical support, including MC10113FN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC10113FN requirements.

6.How does Aetrix verify that MC10113FN is sourced from the original manufacturer or authorized distributors?

All MC10113FN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC10113FN meets industry standards.

7.What is the process for return or replacement of MC10113FN?

All MC10113FN units undergo pre-shipment inspection (PSI). If there is an issue with MC10113FN, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MC10113FN part is unused and in its original packaging.

Return procedure for MC10113FN:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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