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Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

onsemi MC10113P

Name: MC10113P
Brand: onsemi
SKU: MC10113P
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: MC10113P

Manufacturer:: onsemi

Category:: Gates and Inverters

Package:: -

Datasheet:: MC10113P.pdf

Description:: IC GATE XOR 2-INP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

MC10113P from ON Semiconductor is a quad ECL-exclusive OR gate with common active-low enable, designed for high-speed digital comparison and arithmetic logic in MECL 10,000-series systems. It delivers 2.5 ns typical propagation delay, 2.0 ns typical rise/fall time (20–80%), and operates across –30°C to +85°C with –5.2 V VEE supply. Used in 4-bit equality comparators where wire-ORed outputs generate A = B logic.

For engineers reviewing the MC10113P datasheet, pinout, applications, or equivalent options, this page provides verified package mapping (PDIP-16), confirmed ECL-level voltage thresholds (VOH = –0.890 V, VOL = –1.675 V at +25°C), thermal-rated power dissipation (175 mW typ), and functional validation for wire-OR comparison architectures.

Technical Context

The MC10113P implements four independent ECL XOR gates sharing a single active-low enable input (Pin 9), enabling synchronous gating of all outputs. Its differential ECL output structure supports direct wire-OR connection without external pull-ups, allowing compact 4-bit equality detection (A = B) with one output node.

Designed for the MECL 10,000 family, it requires –5.2 V VEE (Pin 8), +VCC1 (Pin 1), and +VCC2 (Pin 16) biasing, with logic thresholds referenced to VEE. Input current is specified at ±0.5 µA (IinL) and up to 870 µA (IinH), and outputs drive 50 Ω loads terminated to –2.0 V per JEDEC-compliant test conditions.

Key Specifications

Parameter	Value and Actual Design Meaning
Propagation Delay	2.5 ns typical (tpd), measured under 50 Ω load to –2.0 V; enables sub-400 MHz toggle-rate operation in critical path logic.
Rise/Fall Time	2.0 ns typical (20–80%), ensuring clean edge integrity for inter-gate timing in pipelined ECL systems.
Output Logic Levels	VOH = –0.890 V, VOL = –1.675 V (at +25°C); compatible with standard MECL 10,000 input thresholds (VIHA = –1.105 V, VILA = –1.475 V).
Supply Configuration	VEE = –5.2 V (Pin 8), VCC1 = Pin 1, VCC2 = Pin 16; dual positive rails support internal bias generation and output stage headroom.
Power Dissipation	175 mW typical per package (no load); thermally validated for continuous operation across –30°C to +85°C ambient.
Operating Temperature	–30°C to +85°C; fully characterized across all electrical parameters per Rev. 7 datasheet test limits.

Pinout & Package

MC10113P is supplied in a 16-pin plastic dual-in-line package (PDIP-16, Case 648–08), with 0.300-inch row spacing and through-hole mounting compatibility.

Pin/Terminal	Circuit Role	Design Meaning
1, 16	VCC1 / VCC2	Positive supply rails for internal bias and output stages; decoupling required at both pins for noise immunity.
8	VEE	Negative supply (–5.2 V); reference for all ECL logic levels and termination; must be low-impedance.
9	ENABLE (active low)	Common gate enable; pulls all four XOR outputs to logic LOW when asserted; open-collector compatible.
2, 3, 14, 15	AOUT, BOUT, COUT, DOUT	Differential ECL outputs; wire-ORable without external components for 4-bit equality detection (A=B).
4, 5, 6, 7, 10, 11, 12, 13	AIN/BIN, CIN/DIN pairs	Eight dedicated XOR inputs (two per gate); each pair drives one exclusive-OR function with defined VIH/VIL thresholds.

Key Features

Feature	Design Value
Quad XOR with shared enable	Single-pin control synchronizes all four gates-reduces control logic overhead in comparator and parity circuits.
Wire-ORable outputs	Eliminates need for external OR gates or pull-up resistors in A=B detection, reducing component count and propagation delay.
ECL 10,000 family compliance	Guaranteed interoperability with MC10100-series drivers, receivers, and flip-flops using identical voltage thresholds and loading rules.
High-speed timing performance	2.5 ns tpd and 2.0 ns tr/tf enable use in >300 MHz clock domains and real-time data path comparison.

Applications

High-Speed Digital Comparator	MECL-Based Parity Generator
Use Scenario: Detecting equality between two 4-bit parallel data buses in real-time instrumentation front-ends. IC Role / Device Role / Timing Role: Performs bitwise XOR then wire-ORs results to produce single A=B flag within one propagation delay. Use Value: Achieves full 4-bit comparison in 2.5 ns-enabling cycle-accurate bus arbitration and error detection in <10 ns windows.	Use Scenario: Generating odd/even parity bits for 4-bit data words in telecom line interface modules. IC Role / Device Role / Timing Role: Each XOR gate computes bit-pair parity; outputs combined via wire-OR to yield final parity signal. Use Value: Delivers deterministic parity output with no added gate delay beyond intrinsic tpd-critical for synchronous serial framing.
Programmable Logic Array (PLA) Core	ECL Test Equipment Signal Conditioning
Use Scenario: Implementing product-term logic in field-replaceable PLAs for military avionics control units. IC Role / Device Role / Timing Role: Serves as configurable XOR cell in AND-OR-XOR PLA architecture; enable pin allows dynamic term masking. Use Value: Enables reconfigurable logic behavior without PCB change-supporting multiple mission profiles via enable sequencing.	Use Scenario: Level-shifting and phase-sensitive comparison of high-frequency test signals in automated RF test benches. IC Role / Device Role / Timing Role: Compares reference and DUT waveforms at ECL speed; outputs feed high-bandwidth latch and analyzer inputs. Use Value: Maintains sub-nanosecond timing correlation between channels-essential for jitter and skew measurement accuracy.

High-Speed Digital Comparator

MECL-Based Parity Generator

Use Scenario: Detecting equality between two 4-bit parallel data buses in real-time instrumentation front-ends.

IC Role / Device Role / Timing Role: Performs bitwise XOR then wire-ORs results to produce single A=B flag within one propagation delay.

Use Value: Achieves full 4-bit comparison in 2.5 ns-enabling cycle-accurate bus arbitration and error detection in <10 ns windows.

Use Scenario: Generating odd/even parity bits for 4-bit data words in telecom line interface modules.

IC Role / Device Role / Timing Role: Each XOR gate computes bit-pair parity; outputs combined via wire-OR to yield final parity signal.

Use Value: Delivers deterministic parity output with no added gate delay beyond intrinsic tpd-critical for synchronous serial framing.

Programmable Logic Array (PLA) Core

ECL Test Equipment Signal Conditioning

Use Scenario: Implementing product-term logic in field-replaceable PLAs for military avionics control units.

IC Role / Device Role / Timing Role: Serves as configurable XOR cell in AND-OR-XOR PLA architecture; enable pin allows dynamic term masking.

Use Value: Enables reconfigurable logic behavior without PCB change-supporting multiple mission profiles via enable sequencing.

Use Scenario: Level-shifting and phase-sensitive comparison of high-frequency test signals in automated RF test benches.

IC Role / Device Role / Timing Role: Compares reference and DUT waveforms at ECL speed; outputs feed high-bandwidth latch and analyzer inputs.

Use Value: Maintains sub-nanosecond timing correlation between channels-essential for jitter and skew measurement accuracy.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad XOR gate applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MC10113L	Ceramic DIP-16 (Case 620), higher thermal stability, rated for –55°C to +125°C operation.	Better suited for extended temperature environments (e.g., aerospace, downhole tools) where PDIP mechanical reliability is insufficient.	Select MC10113L when operating beyond +85°C or requiring hermetic sealing and lower thermal resistance.
MC10113FN	PLCC-20 (Case 775), surface-mount, 20-pin footprint with dedicated VCC/VEE pins per quadrant and improved high-frequency layout.	Enables dense PCB layouts in automated assembly; supports tighter impedance control for >500 MHz signal routing.	Choose MC10113FN for volume production with SMT lines or when board space and RF performance outweigh through-hole serviceability needs.

Compared with MC10113L and MC10113FN, the MC10113P offers lowest-cost through-hole implementation with full functional equivalence, optimized for industrial-grade temperature range and manual or semi-automated assembly where thermal margin and packaging robustness are balanced.

Availability

MC10113P is available at Aetrix Electronics and suitable for high-speed digital comparators, MECL-based parity generators, programmable logic array cores, and ECL test equipment signal conditioning requiring stable component supply across industrial and legacy system refresh programs.

Supply support for MC10113P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

ON Semiconductor (formerly part of Motorola Semiconductor) is a global supplier of high-performance silicon solutions for automotive, industrial, cloud, and communications markets, with deep heritage in bipolar and ECL logic design.

The MC10113P belongs to the MECL 10,000 series-a family engineered for ultra-high-speed digital systems requiring sub-3 ns propagation delays, precise threshold control, and interoperability across logic, memory, and interface functions.

FAQ

What is the recommended termination for MC10113P outputs?

MC10113P outputs must be terminated to –2.0 V through a 50 Ω resistor per JEDEC test conditions. This ensures correct logic level definition, minimizes reflections on high-speed traces, and maintains specified VOH/VOL and switching times. Improper termination causes timing skew and logic errors in wire-OR configurations.

Does MC10113P support true complementary ECL outputs?

No. The MC10113P provides single-ended ECL outputs (e.g., AOUT, BOUT). It does not include complementary (true/complement) output pairs. Each XOR gate has one output only; differential signaling requires external pairing or use of dedicated ECL differential drivers.

Can MC10113P outputs be directly connected to TTL or CMOS inputs?

No. MC10113P outputs operate at ECL voltage levels (e.g., VOH ≈ –0.89 V, VOL ≈ –1.68 V), which are incompatible with TTL (0 V / +5 V) or CMOS (0 V / VDD) logic families. Level translation via dedicated ECL-to-TTL translators (e.g., MC10124) is required for interfacing.

What is the maximum fan-out capability of the MC10113P enable input?

The MC10113P enable input (Pin 9) draws up to 870 µA (IinH) at +25°C. With standard MECL 10,000-series driver output capability (~–40 mA sink), it can drive ≥40 MC10113P enable inputs without degradation-verified by IinH/IinL specs and fan-out calculations in the Rev. 7 datasheet.

Is MC10113P pin-compatible with other MECL quad XOR devices like MC10184?

No. MC10113P uses a unique 16-pin PDIP pinout optimized for wire-OR comparison (e.g., outputs on Pins 2,3,14,15; inputs distributed across 4–7,10–13). MC10184 is a dual XOR with different pin assignment, supply configuration, and no shared enable-making them functionally and physically non-interchangeable.

MC10113P Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: *

Package/Case:: -

Packaging:: Bulk

Product Status:: Active

Logic Type:: -

Number of Circuits:: -

Number of Inputs:: -

Features:: -

Voltage - Supply:: -

Current - Quiescent (Max):: -

Current - Output High, Low:: -

Input Logic Level - Low:: -

Input Logic Level - High:: -

Max Propagation Delay @ V, Max CL:: -

Operating Temperature:: -

Grade:: -

Qualification:: -

Mounting Type:: -

Supplier Device Package:: -

MC10113P FAQ

1.How can I place an order for MC10113P through Aetrix?

Please submit a Request for Quotation (RFQ) for MC10113P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MC10113P reliable?

The price and inventory of MC10113P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC10113P is usually 5 days.

3.What payment methods are accepted for MC10113P?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC10113P transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MC10113P?

MC10113P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MC10113P order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MC10113P?

For technical support, including MC10113P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC10113P requirements.

6.How does Aetrix verify that MC10113P is sourced from the original manufacturer or authorized distributors?

All MC10113P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC10113P meets industry standards.

7.What is the process for return or replacement of MC10113P?

All MC10113P units undergo pre-shipment inspection (PSI). If there is an issue with MC10113P, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MC10113P part is unused and in its original packaging.

Return procedure for MC10113P:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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