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Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

onsemi MC10117L

Name: MC10117L
Brand: onsemi
SKU: MC10117L
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: MC10117L

Manufacturer:: onsemi

Category:: Gates and Inverters

Package:: -

Datasheet:: MC10117L.pdf

Description:: IC GATE OR/AND INVERTER

Quantity:: RFQ Add To RFQ list

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Product details

Overview

MC10117L from ON Semiconductor is a dual 2-wide 2–3-input OR–AND/OR–AND–Invert gate in ECL logic, designed for high-speed digital multiplexing and data distribution. It features 2.3 ns typical propagation delay, 2.2 ns typical rise/fall time (20%–80%), and operates with V_CC1 = +1.11 V, V_CC2 = +2.0 V, and V_EE = –5.2 V.

For engineers reviewing the MC10117L datasheet, pinout, applications, or equivalent options, this page delivers verified electrical timing, dual-gate logic topology, CDIP-16 package mapping, thermal-rated power dissipation (100 mW typ), and MECL 10,000-series interface compatibility - all critical for high-speed control path design.

Technical Context

The MC10117L implements two independent OR–AND–Invert logic functions in a single monolithic MECL 10,000-series device. Each gate accepts two 2-input OR terms feeding a shared 3-input AND stage, with Pin 9 serving as common input to both gates.

It operates under split-supply ECL conditions: V_CC1 (Pin 1) and V_CC2 (Pin 16) supply positive rails, while V_EE (Pin 8) sets the negative reference at –5.2 V. Outputs are terminated to –2.0 V via 50 Ω, enabling precise 20–80% transition measurement per JEDEC-compliant test setup.

Key Specifications

Parameter	Value and Actual Design Meaning
Propagation Delay	2.3 ns typical - enables ≤435 MHz toggle rate in cascaded logic paths
Rise/Fall Time	2.2 ns typical (20%–80%) - supports clean signal edges into 50 Ω loads
Supply Voltages	V_CC1 = +1.11 V, V_CC2 = +2.0 V, V_EE = –5.2 V - defines MECL 10K-compatible biasing
Output Voltage Logic 1	–0.780 Vdc typ at +25°C - ensures valid high-state margin above VOHA threshold (–0.980 V)
Output Voltage Logic 0	–1.675 Vdc typ at +25°C - maintains >0.7 V noise margin below VOLA threshold (–1.630 V)
Power Dissipation	100 mW typical per package (no load) - constrains thermal design in dense PCB layouts

Pinout & Package

Ceramic Dual-In-Line Package (CDIP–16), Case 620, 0.3-inch width, with hermetic sealing suitable for military and high-reliability industrial environments.

Pin/Terminal	Circuit Role	Design Meaning
1	V_CC1	+1.11 V primary positive supply rail for Gate A logic
2, 3	A_OUT	Differential output pair for Gate A (OR–AND–Invert function)
4, 5, 12, 13	A1IN, A2IN	Two 2-input OR term inputs for Gate A; Pins 4/5 and 12/13 form separate OR legs
6, 7, 10, 11	B1IN, B2IN	Two 2-input OR term inputs for Gate B; Pins 6/7 and 10/11 form separate OR legs
8	V_EE	–5.2 V common emitter reference for both gates
9	COMMON	Shared input terminal connected to both Gate A and Gate B AND stages
14, 15	B_OUT	Differential output pair for Gate B (OR–AND–Invert function)
16	V_CC2	+2.0 V secondary positive supply rail for Gate B logic

Key Features

Feature	Design Value
Dual independent OR–AND–Invert logic blocks	Enables compact implementation of 2-channel priority encoding or dual-path data selection without external gating
2.3 ns propagation delay (typ)	Supports sub-500 ps setup/hold windows in synchronous bus arbitration circuits
MECL 10,000 series DC compliance	Guarantees interoperability with legacy ECL systems including MC10100/MC10116 families
Common input pin (Pin 9)	Reduces interconnect count when synchronizing enable/control signals across both gates

Applications

High-Speed Data Multiplexer	Digital Bus Arbitration
Use Scenario: Selecting between two parallel 8-bit data streams in real-time instrumentation front-ends. IC Role / Device Role / Timing Role: Dual OR–AND–Invert gate performs simultaneous 2:1 selection on upper and lower nibbles using shared enable (Pin 9). Use Value: 2.3 ns t_pd ensures <1 ns skew between channels, preserving data coherency at 200+ Mbps aggregate rates.	Use Scenario: Resolving contention among three microprocessor buses sharing a common memory controller. IC Role / Device Role / Timing Role: Implements priority encoder logic where Gate A resolves Bus A/B conflict and Gate B resolves Bus C/enable state. Use Value: Differential outputs drive 50 Ω transmission lines directly, eliminating need for external line drivers in backplane designs.
Phase Alignment Circuit	ECL Clock Distribution Node
Use Scenario: Aligning asynchronous trigger pulses from multiple sensors before feeding to a time-to-digital converter. IC Role / Device Role / Timing Role: Uses common Pin 9 as synchronized strobe to OR–AND–Invert both input pulse trains, generating aligned output windows. Use Value: Sub-3 ns delay variation across temperature (–30°C to +85°C) maintains ±50 ps alignment tolerance.	Use Scenario: Fan-out buffering of a master ECL clock to four downstream logic clusters in radar signal processing. IC Role / Device Role / Timing Role: Each gate drives one differential clock pair; shared V_EE (Pin 8) minimizes ground bounce-induced jitter. Use Value: 100 mW typical package power enables stable operation without forced-air cooling in sealed enclosures.

High-Speed Data Multiplexer

Digital Bus Arbitration

Use Scenario: Selecting between two parallel 8-bit data streams in real-time instrumentation front-ends.

IC Role / Device Role / Timing Role: Dual OR–AND–Invert gate performs simultaneous 2:1 selection on upper and lower nibbles using shared enable (Pin 9).

Use Value: 2.3 ns t_pd ensures <1 ns skew between channels, preserving data coherency at 200+ Mbps aggregate rates.

Use Scenario: Resolving contention among three microprocessor buses sharing a common memory controller.

IC Role / Device Role / Timing Role: Implements priority encoder logic where Gate A resolves Bus A/B conflict and Gate B resolves Bus C/enable state.

Use Value: Differential outputs drive 50 Ω transmission lines directly, eliminating need for external line drivers in backplane designs.

Phase Alignment Circuit

ECL Clock Distribution Node

Use Scenario: Aligning asynchronous trigger pulses from multiple sensors before feeding to a time-to-digital converter.

IC Role / Device Role / Timing Role: Uses common Pin 9 as synchronized strobe to OR–AND–Invert both input pulse trains, generating aligned output windows.

Use Value: Sub-3 ns delay variation across temperature (–30°C to +85°C) maintains ±50 ps alignment tolerance.

Use Scenario: Fan-out buffering of a master ECL clock to four downstream logic clusters in radar signal processing.

IC Role / Device Role / Timing Role: Each gate drives one differential clock pair; shared V_EE (Pin 8) minimizes ground bounce-induced jitter.

Use Value: 100 mW typical package power enables stable operation without forced-air cooling in sealed enclosures.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual OR–AND–Invert logic applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MC10116L	Single 2-wide 2–3-input OR–AND–Invert gate; identical timing (2.3 ns t_pd) and supply specs	Requires two units for dual-channel use; increases board area and power by ~2×	Select MC10116L only when layout constraints favor modular gate placement over integrated dual functionality
SN55117J	Military-grade version with extended temperature range (–55°C to +125°C); same pinout and logic function	Qualified for aerospace and defense platforms requiring MIL-PRF-38535 compliance	Choose SN55117J when environmental qualification outweighs cost premium and commercial temp range suffices

Compared with MC10116L, the MC10117L reduces component count and interconnect complexity for dual-path logic; versus SN55117J, it trades extended temperature capability for lower procurement cost and broader commercial availability.

Availability

MC10117L is available at Aetrix Electronics and suitable for high-speed data multiplexing, digital bus arbitration, and ECL clock distribution requiring stable component supply across industrial, test & measurement, and avionics programs.

Supply support for MC10117L includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

ON Semiconductor (formerly Semiconductor Components Industries, LLC) is a global supplier of energy-efficient semiconductor components for automotive, industrial, cloud computing, and IoT applications.

The MC10117L belongs to the MECL 10,000 family - engineered specifically for high-speed, low-skew digital control in mission-critical timing and data routing systems where nanosecond-level predictability is required.

FAQ

What logic family does the MC10117L belong to, and what are its key voltage requirements?

The MC10117L is a MECL 10,000-series device requiring three supply rails: V_CC1 = +1.11 V (Pin 1), V_CC2 = +2.0 V (Pin 16), and V_EE = –5.2 V (Pin 8). Its logic thresholds are defined relative to V_EE, with VOH ≈ –0.78 V and VOL ≈ –1.675 V at +25°C. These voltages ensure compatibility with standard ECL termination schemes using –2.0 V bias and 50 Ω loads.

How is the common input (Pin 9) used in the MC10117L's dual-gate architecture?

Pin 9 serves as a shared input terminal connected internally to the AND stage of both Gate A and Gate B in the MC10117L. This allows a single control signal - such as an enable, strobe, or reset - to simultaneously gate the output of both OR–AND–Invert functions without external wiring. It reduces fan-out loading and eliminates skew between channels caused by discrete signal distribution.

What is the maximum operating temperature range specified for the MC10117L?

The MC10117L is characterized from –30°C to +85°C, with full electrical specifications guaranteed across this range. Propagation delay remains within 1.4–3.9 ns, and output voltage levels maintain defined margins relative to VOHA (–0.980 V) and VOLA (–1.630 V) limits. This range supports industrial and commercial applications but excludes extended military or automotive under-hood environments.

Does the MC10117L require external termination, and if so, what configuration is specified?

Yes, the MC10117L requires 50 Ω termination to –2.0 V for each differential output pair (Pins 2/3 and 14/15), as defined in the official test setup. This configuration ensures proper signal integrity, controls edge rates (2.2 ns rise/fall), and meets the 2.3 ns typical propagation delay specification. Failure to terminate correctly results in ringing, degraded noise margin, and timing violations.

Is the MC10117L pin-compatible with other devices in the MC101xx series?

The MC10117L shares the CDIP-16 footprint and core supply pin assignments (V_CC1, V_CC2, V_EE) with MC10116L and MC10118L, but logic function and pin mapping differ. While Pin 9 is common input in MC10117L, MC10116L has no common pin and MC10118L implements dual 2-input XOR gates. Direct substitution is not supported without circuit redesign and timing validation.

MC10117L Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: *

Package/Case:: -

Packaging:: Bulk

Product Status:: Active

Logic Type:: -

Number of Circuits:: -

Number of Inputs:: -

Features:: -

Voltage - Supply:: -

Current - Quiescent (Max):: -

Current - Output High, Low:: -

Input Logic Level - Low:: -

Input Logic Level - High:: -

Max Propagation Delay @ V, Max CL:: -

Operating Temperature:: -

Grade:: -

Qualification:: -

Mounting Type:: -

Supplier Device Package:: -

MC10117L FAQ

1.How can I place an order for MC10117L through Aetrix?

Please submit a Request for Quotation (RFQ) for MC10117L on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MC10117L reliable?

The price and inventory of MC10117L are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC10117L is usually 5 days.

3.What payment methods are accepted for MC10117L?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC10117L transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MC10117L?

MC10117L orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MC10117L order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MC10117L?

For technical support, including MC10117L datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC10117L requirements.

6.How does Aetrix verify that MC10117L is sourced from the original manufacturer or authorized distributors?

All MC10117L products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC10117L meets industry standards.

7.What is the process for return or replacement of MC10117L?

All MC10117L units undergo pre-shipment inspection (PSI). If there is an issue with MC10117L, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MC10117L part is unused and in its original packaging.

Return procedure for MC10117L:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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