onsemi MC10117P

Overview

MC10117P from ON Semiconductor is a dual 2-wide 2–3-input OR–AND/OR–AND–Invert gate in MECL 10,000 logic family, designed for high-speed digital multiplexing and data distribution. It features 2.3 ns typical propagation delay, 2.2 ns typical rise/fall time (20%–80%), –5.2 V VEE supply, and operates across –30°C to +85°C.

For engineers reviewing the MC10117P datasheet, pinout, applications, or equivalent options, this page delivers verified electrical parameters, dual-gate logic topology, PDIP-16 package mapping, thermal performance limits, and direct alternatives for ECL-based control path design.

Technical Context

The MC10117P implements two independent OR–AND–Invert logic gates sharing VCC1 (Pin 1), VCC2 (Pin 16), and VEE (Pin 8). Each gate accepts two 2-input OR terms feeding a common AND–Invert output stage, with Pin 9 serving as shared input for both gates' second OR term.

It operates strictly in negative ECL mode: VOH = –0.78 Vdc (typ), VOL = –1.675 Vdc (typ) at +25°C with 50 Ω load to –2.0 V, and requires termination to –2.0 V for valid switching. Input thresholds are VIHA = –1.105 Vdc (min), VILA = –1.475 Vdc (max) at +25°C.

Key Specifications

Pinout & Package

MC10117P is packaged in a 16-pin plastic dual-in-line package (PDIP-16), Case 648–08, with 0.300-inch lead spacing and through-hole mounting compatibility.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ECL logic gate applications.

Compared with MC10117P, MC10116P reduces gate count but sacrifices concurrent path handling, while SN55L117J maintains full functional equivalence with enhanced reliability screening-neither is pin-compatible drop-in replacements without verifying qualification scope and procurement chain traceability.

Availability

MC10117P is available at Aetrix Electronics and suitable for telecom multiplexer control, digital test equipment data routing, and radar signal processing pipeline applications requiring stable component supply across extended temperature ranges and legacy ECL system refresh cycles.

Supply support for MC10117P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

ON Semiconductor (formerly part of Motorola Semiconductor) is a global supplier of high-performance silicon solutions for automotive, industrial, cloud computing, and communications markets.

The MC10117P belongs to the MECL 10,000 series - a family engineered for ultra-high-speed digital control in mission-critical infrastructure where nanosecond timing determinism and noise immunity are non-negotiable.

FAQ

What logic family does the MC10117P belong to, and what voltage levels define its operation?

The MC10117P belongs to the MECL 10,000 family and operates with VCC1 and VCC2 tied to ground, and VEE at –5.2 V. Its logic-high output (VOH) is –0.78 Vdc (typ), logic-low (VOL) is –1.675 Vdc (typ) at +25°C, with input thresholds VIHA = –1.105 Vdc (min) and VILA = –1.475 Vdc (max). These values define its negative-referenced ECL signaling interface, requiring proper termination to –2.0 V for valid switching.

How many logic gates does the MC10117P contain, and how are their inputs structured?

The MC10117P contains two independent OR–AND–Invert gates. Each gate has two 2-input OR terms feeding an AND–Invert output stage. Gate A uses Pins 4–7 and 9; Gate B uses Pins 10–13 and 9. Pin 9 is explicitly designated as common to both gates, enabling shared control signal routing without external fanout.

What is the typical propagation delay of the MC10117P, and under what test conditions is it measured?

The MC10117P has a typical propagation delay of 2.3 ns, measured under standard MECL 10,000 test conditions: VEE = –5.2 V, outputs terminated to –2.0 V via 50 Ω resistors, ambient temperature +25°C, and driving a 50 Ω load. This value applies to t4+2+, t4–2–, t4+3–, and t4–3+ transitions as specified in the official ON Semiconductor datasheet Rev. 7.

Does the MC10117P support operation across industrial temperature ranges, and what are its thermal limits?

Yes, the MC10117P is rated for operation from –30°C to +85°C, validated per JEDEC JESD22-A108 thermal cycling and steady-state bias testing. Electrical characteristics including VOH, VOL, tpd, and IinH/IinL are guaranteed across this full range, making MC10117P suitable for industrial PLC backplanes, telecom line cards, and radar front-end modules without derating.

What package type is used for the MC10117P, and how does it differ from other variants like MC10117L or MC10117FN?

The MC10117P uses a 16-pin plastic dual-in-line package (PDIP-16), Case 648–08. In contrast, MC10117L uses a ceramic DIP (CDIP-16, Case 620–10) for hermetic sealing and higher thermal conductivity, while MC10117FN uses a 20-pin plastic leaded chip carrier (PLCC-20, Case 775–02) for surface-mount assembly. All share identical logic functionality and DC/AC specifications, differing only in mechanical form factor and thermal profile.