onsemi MC10H104MG
- Part No.:
- MC10H104MG
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 16-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
MC10H104MG.pdf
- Description:
- IC GATE AND 4CH 2-INP 16SOEIAJ
- Quantity:
- Payment:

- Shipping:

Inventory:1,325
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MC10H104MG from ON Semiconductor is a quad 2-input MECL 10H™ AND gate with one gate providing both AND and NAND outputs, 1.0 ns typical propagation delay, −5.2 V VEE supply, and SOEIAJ-16 surface-mount package. It operates from 0°C to +75°C and delivers 25 mW per gate power dissipation in high-speed digital logic systems requiring ECL-level timing precision.
For engineers reviewing the MC10H104MG datasheet, pinout, applications, or equivalent options, this part serves as a drop-in performance upgrade over MECL 10K AND gates in telecom clock distribution, high-speed test equipment, and digital signal processing front-ends where sub-2 ns timing margins are critical.
Technical Context
The MC10H104MG implements four independent 2-input AND functions using emitter-coupled logic with differential input thresholds and complementary outputs on Gate 1. Its voltage-compensated design maintains stable VIH/VIL across temperature and supply variation.
All gates share common VCC1 (Pin 1), VCC2 (Pin 16), and VEE (Pin 8) rails. Output termination requires 50 Ω to −2.0 V for guaranteed AC performance, and inputs accept standard MECL 10K logic levels while delivering improved 150 mV noise margin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Propagation Delay | 0.45–1.9 ns (max at 75°C); enables ≤500 MHz toggle rates in synchronous logic paths |
| Supply Voltage | VEE = −5.2 V ±5%; requires dual-rail biasing with VCC1/VCC2 at ground reference |
| Output Voltage Swing | VOH = −0.92 to −0.735 V, VOL = −1.95 to −1.60 V; defines 1.0–1.2 V differential swing for noise-immune signaling |
| Input Thresholds | VIH = −1.07 to −0.735 V, VIL = −1.95 to −1.45 V; ensures robust logic discrimination under thermal drift |
| Power Dissipation | 25 mW per gate; matches MECL 10K consumption while halving delay, easing thermal management |
| Operating Temperature | 0°C to +75°C; validated for industrial-grade digital subsystems without derating |
Pinout & Package
MC10H104MG uses the SOEIAJ-16 (JEDEC MS-012AC) 16-pin surface-mount package: 10.5 mm × 7.6 mm body, 1.27 mm pitch, gull-wing leads, Pb-free finish. Pin 1 is VCC1; Pin 16 is VCC2; Pin 8 is VEE.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 16 | VCC1 / VCC2 | Positive supply terminals (ground-referenced); must be decoupled locally to minimize switching noise |
| 8 | VEE | Negative supply (−5.2 V); common emitter return for all gates; low-inductance connection required |
| 2, 3 / 4, 5 / 6, 7 / 10, 11 | Ain/Bin / Cin/Din / Ein/Fin / Gin/Hin | Differential input pairs for Gates 1–4; each accepts standard MECL 10K logic levels |
| 9, 12 / 13, 14 / 15, 16 | Aout/Bout / Cout/Dout / Eout/Fout / Gout/Hout | Complementary AND/NAND outputs (Gate 1 only has both); others provide single-ended AND output |
Key Features
| Feature | Design Value |
|---|---|
| 1.0 ns typical propagation delay | Enables sub-1 GHz logic path timing in high-speed serial interface state machines and clock dividers |
| MECL 10K pinout and functional compatibility | Allows direct PCB replacement of legacy 10K AND gates without layout or firmware changes |
| 150 mV improved noise margin | Reduces susceptibility to crosstalk and supply bounce in dense backplane routing environments |
| Voltage-compensated input stage | Maintains consistent switching thresholds across −5.2 V supply tolerance and temperature extremes |
Applications
| Telecom Clock Distribution | Digital Test Equipment |
|---|---|
|
Use Scenario: Synchronizing multiple SERDES lanes in OC-192 line cards using distributed ECL clocks. IC Role / Device Role / Timing Role: Quad AND gate performing clock enable gating and phase alignment logic for jitter-sensitive data paths. Use Value: 1.0 ns delay consistency ensures <±5 ps skew between gated clock branches, preserving eye opening. |
Use Scenario: Generating precise strobe and trigger signals in automated test equipment (ATE) pattern generators. IC Role / Device Role / Timing Role: High-speed logic combiner for multi-channel timing control, enabling sub-nanosecond pulse edge placement. Use Value: Guaranteed 1.9 ns max propagation at 75°C allows reliable 400+ MHz pattern rate generation without timing guardbanding. |
| Radar Signal Processing | High-Speed Data Acquisition |
|
Use Scenario: Real-time pulse compression logic in airborne synthetic aperture radar (SAR) front-ends. IC Role / Device Role / Timing Role: AND-based gating of matched filter outputs synchronized to chirp start events. Use Value: 150 mV noise margin prevents false triggers from RF coupling into logic control lines near analog receive chains. |
Use Scenario: Channel selection and sample-enable logic in 1 GS/s digitizers used for oscilloscope and spectrum analyzer platforms. IC Role / Device Role / Timing Role: Synchronous AND gate controlling ADC sampling windows aligned to external reference clocks. Use Value: 25 mW/gate dissipation permits dense integration of 16+ logic channels on compact acquisition PCBs without forced air cooling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 2-input AND gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC100H104M | Higher-speed MECL 100K variant; 0.7 ns typical tpd, −5.2 V VEE, same SOEIAJ-16 package | Requires tighter supply regulation and faster board-level termination; suited for >600 MHz designs | Select when absolute minimum delay is prioritized over power budget and supply simplicity |
| SN74AS1004N | TTL-compatible quad AND with 3.5 ns tpd, +5 V single supply, PDIP-16 package | Not electrically compatible; requires level-shifting and redesign of bias network and termination | Choose only for cost-sensitive, non-ECL systems where speed >200 MHz is sufficient and layout change is acceptable |
Compared with MC100H104M, MC10H104MG trades 0.3 ns delay for broader supply tolerance and simpler thermal design; versus SN74AS1004N, it provides true ECL interoperability and sub-2 ns timing but demands negative supply infrastructure.
Availability
MC10H104MG is available at Aetrix Electronics and suitable for telecom infrastructure, automated test equipment, radar signal processing, and high-speed data acquisition requiring stable component supply and long-term obsolescence management.
Supply support for MC10H104MG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
ON Semiconductor is a global semiconductor supplier focused on energy-efficient electronics, delivering power management, analog, sensor, and logic solutions for automotive, industrial, and communications markets.
The MC10H104MG belongs to the MECL 10H™ family-designed specifically for high-speed digital systems demanding nanosecond-level timing precision, low-noise operation, and backward compatibility with legacy ECL logic architectures.
FAQ
What is the recommended termination for MC10H104MG outputs?
MC10H104MG outputs must be terminated with a 50 Ω resistor to −2.0 V to meet AC specifications including propagation delay and rise/fall times. This termination ensures proper signal integrity and impedance matching in ECL transmission lines. Failure to apply correct termination will result in degraded timing performance and increased jitter. The MC10H104MG datasheet explicitly specifies this condition for all AC parameter validation.
Does MC10H104MG support true differential input operation?
MC10H104MG accepts standard MECL 10K differential input voltages (VIH/VIL) but does not include internal differential receivers-it relies on externally referenced complementary inputs. Each AND gate uses two single-ended inputs referenced to VEE, with logic thresholds defined relative to the −5.2 V rail. The MC10H104MG is not a fully differential-input device like LVDS or PECL ICs, but its input structure is optimized for noise rejection in balanced ECL signaling environments.
Can MC10H104MG replace MC10K104 in existing designs without modification?
Yes-MC10H104MG is a functional and pinout-compatible upgrade to MC10K104, offering identical SOEIAJ-16 packaging, identical VCC/VEE pin assignments, and identical logic function mapping. Its 100% improvement in propagation delay occurs without increasing supply current, making it a direct drop-in replacement. The MC10H104MG maintains full DC and AC interoperability with legacy MECL 10K systems.
What is the maximum operating junction temperature for MC10H104MG?
The MC10H104MG has a specified operating ambient temperature range of 0°C to +75°C. With its 25 mW per gate power dissipation and SOEIAJ-16 thermal characteristics, the junction temperature remains within safe limits under standard PCB copper pour and natural convection conditions. Derating is not required within this ambient range, and the MC10H104MG does not specify a separate TJ max beyond the ambient limit.
Is MC10H104MG RoHS compliant?
Yes-MC10H104MG is manufactured in a Pb-free (RoHS-compliant) configuration, as indicated by the "G" suffix and confirmed in the ON Semiconductor ordering information table. The device meets JEDEC J-STD-609 Category 1 marking requirements and complies with EU RoHS Directive 2011/65/EU. Full compliance documentation, including material declarations, is available through ON Semiconductor's official product page for MC10H104MG.
MC10H104MG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 10H
- Package/Case:
- 16-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- AND Gate
- Number of Circuits:
- 4
- Number of Inputs:
- 2
- Features:
- 1 of 4 AND/NAND Output
- Voltage - Supply:
- -4.94V ~ -5.46V
- Current - Quiescent (Max):
- -
- Current - Output High, Low:
- 50mA, 50mA
- Input Logic Level - Low:
- -1.48V
- Input Logic Level - High:
- -1.13V
- Max Propagation Delay @ V, Max CL:
- 1.75ns @ -5.2V, -
- Operating Temperature:
- 0°C ~ 75°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOEIAJ
MC10H104MG FAQ
1.How can I place an order for MC10H104MG through Aetrix?
Please submit a Request for Quotation (RFQ) for MC10H104MG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MC10H104MG reliable?
The price and inventory of MC10H104MG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC10H104MG is usually 5 days.
3.What payment methods are accepted for MC10H104MG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC10H104MG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MC10H104MG?
MC10H104MG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MC10H104MG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MC10H104MG?
For technical support, including MC10H104MG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC10H104MG requirements.
6.How does Aetrix verify that MC10H104MG is sourced from the original manufacturer or authorized distributors?
All MC10H104MG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC10H104MG meets industry standards.
7.What is the process for return or replacement of MC10H104MG?
All MC10H104MG units undergo pre-shipment inspection (PSI). If there is an issue with MC10H104MG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MC10H104MG part is unused and in its original packaging.
Return procedure for MC10H104MG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MC10H104MG Tags
-
SN74LVC1G14DBVR
Texas Instruments
-
SN74LVC1G14DCKR
Texas Instruments
-
SN74AHC1G14DBVR
Texas Instruments
-
SN74LVC1G08DBVR
Texas Instruments
-
SN74LVC1G08DCKR
Texas Instruments
-
SN74LVC1G32DCKR
Texas Instruments
-
SN74LVC1G04DBVR
Texas Instruments
.jpg)
-
74LVC1G08GW,125
Nexperia USA Inc.
-
SN74LVC1G04DCKR
Texas Instruments
-
SN74AHC1G08DBVR
Texas Instruments
-
SN74LVC1G32DBVR
Texas Instruments
-
SN74AHCT1G08DBVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

