onsemi MC10H106FNR2
- Part No.:
- MC10H106FNR2
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 20-LCC (J-Lead)
- Datasheet:
-
MC10H106FNR2.pdf
- Description:
- IC GATE NOR 3CH 4/3/3-INP 20PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:5,500
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MC10H106FNR2 from ON Semiconductor is a triple 4−3−3-input ECL NOR gate in PLLC-20 package, delivering 1.0 ns typical propagation delay, −5.2 V VEE supply operation, and MECL 10K pinout compatibility for high-speed logic interfacing in telecom line cards and test equipment.
For engineers reviewing the MC10H106FNR2 datasheet, pinout, applications, or equivalent options, this page provides verified electrical specs, terminal roles, thermal-rated AC performance, and direct alternatives for ECL logic replacement in legacy 10K-system upgrades.
Technical Context
The MC10H106FNR2 implements three independent NOR gates with asymmetric input counts (four inputs on A-group, three each on B- and C-groups), all operating from a single −5.2 V VEE supply with VCC1 and VCC2 referenced to ground. It maintains strict MECL 10K voltage thresholds while improving noise margin to 150 mV across 0°C to +75°C.
Its propagation delay (0.5–1.55 ns) and rise/fall times (0.5–1.9 ns) are characterized with 50 Ω termination to −2.0 V, requiring transverse airflow >500 lfpm for guaranteed AC specs. The device draws ≤23 mA supply current and supports DC-coupled interconnects without level-shifting.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Propagation Delay | 0.5–1.55 ns over temperature; enables sub-1 GHz clock domain synchronization |
| Supply Voltage (VEE) | −5.2 V ±5%; requires precision negative regulator, not compatible with −4.5 V or −5.0 V rails |
| Output Voltage (VOH/VOL) | −1.02 to −0.735 V (high), −1.95 to −1.60 V (low); defines valid MECL logic swing for receiver compatibility |
| Input Voltage Thresholds | VIH = −1.17 to −0.735 V, VIL = −1.95 to −1.45 V; ensures noise immunity ≥150 mV across full range |
| Operating Temperature | 0°C to +75°C; validated only for commercial/industrial ambient, not extended or military grade |
| Power Supply Current | ≤23 mA at 25°C; fixed quiescent draw independent of toggle rate, critical for thermal budgeting |
Pinout & Package
MC10H106FNR2 uses the 20-lead Plastic Leaded Chip Carrier (PLLC-20, Case 775), surface-mount package with gull-wing leads, 0.050" pitch, and exposed thermal pad. Dimensions: 0.385" × 0.385" × 0.032" (9.78 mm × 9.78 mm × 0.81 mm).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 16 | VCC1 / VCC2 | Ground-referenced power pins; both must be connected to 0 V for proper biasing of internal emitter followers |
| 8 | VEE | Negative supply rail (−5.2 V); primary current return path and logic reference for all gates |
| 2, 3, 4, 5 | Ain1–Ain4 | Four-input NOR group A; all four must be low to assert Aout high (−0.84 V typical) |
| 6, 7, 10 | Bin1–Bin3 | Three-input NOR group B; active-low inputs drive Bout (Pin 9) with same VOH/VOL specs as Aout |
| 11, 12, 13 | Cin1–Cin3 | Three-input NOR group C; outputs on Pin 14 (Cout), electrically identical to Aout/Bout |
| 9, 14, 15 | Aout, Bout, Cout | Complemented outputs; terminated to −2.0 V via 50 Ω for specified AC performance |
Key Features
| Feature | Design Value |
|---|---|
| MECL 10K pinout compatibility | Direct drop-in replacement for MC10106/MC10107 in existing PCB layouts without trace modification |
| 150 mV noise margin | Guaranteed minimum voltage separation between VIH and VIL across full temp/voltage range, enabling robust operation in noisy backplanes |
| Voltage-compensated design | Internal biasing rejects VEE drift up to ±5%, maintaining consistent switching thresholds without external trimming |
| 1.0 ns typical propagation delay | Reduces combinatorial delay by >50% vs. legacy 10K parts, supporting tighter setup/hold timing in high-speed serializers |
Applications
| Telecom Line Card Timing | ATE Pattern Generator Logic |
|---|---|
|
Use Scenario: Synchronizing parallel data lanes in DS3/E3 framer interfaces where deterministic gate delay is required for skew control. IC Role / Device Role / Timing Role: NOR-based glue logic for address decode and strobe generation in multi-chip timing paths. Use Value: 1.0 ns typical tpd ensures <100 ps inter-lane skew across three independent gate groups, meeting SONET OC-48 jitter budgets. |
Use Scenario: Building programmable stimulus engines in automated test equipment that drive DUTs with precise edge-aligned vectors. IC Role / Device Role / Timing Role: Combinational logic element in high-speed pattern sequencers generating >500 MHz test clocks and control signals. Use Value: Sub-1.55 ns max tpd guarantees setup time compliance for flip-flops clocked at 600 MHz, eliminating pipeline bubbles. |
| Radar Pulse Processing | Digital Oscilloscope Trigger Path |
|
Use Scenario: Real-time pulse width discrimination in L-band radar receivers processing short-duration RF bursts. IC Role / Device Role / Timing Role: Fast NOR gate implementing leading/trailing edge detection logic on digitized IF samples. Use Value: 150 mV noise margin prevents false triggers from RF coupling into analog front-end, sustaining >99.9% detection fidelity. |
Use Scenario: Edge-sensitive trigger arbitration in 1 GHz bandwidth digital storage oscilloscopes with multi-channel simultaneous capture. IC Role / Device Role / Timing Role: Glue logic combining channel enable, slope select, and level threshold signals into unified trigger assertion. Use Value: Matched propagation delays across A/B/C groups ensure <50 ps trigger path skew between channels, preserving time-correlation accuracy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ECL NOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC100H106FN | Higher speed grade: 0.7 ns typical tpd, −40°C to +85°C rating, requires −5.0 V VEE | Supports extended temperature industrial deployments but needs tighter VEE regulation | Select when operating beyond +75°C or requiring <0.9 ns max delay; verify VEE stability at −5.0 V |
| SN64EL11D | LVPECL-compatible, 3.3 V supply, 0.8 ns typical tpd, different pinout (SOIC-14) | Enables migration to modern 3.3 V systems but requires PCB redesign and level translation | Choose for new designs targeting LVPECL I/O standards; not suitable for drop-in 10H/10K board replacements |
Compared with MC100H106FN and SN64EL11D, the MC10H106FNR2 uniquely balances legacy MECL 10K compatibility, −5.2 V operation, and 1.0 ns performance-making it the only option for cost-sensitive upgrades of deployed 10K-based systems without layout changes.
Availability
MC10H106FNR2 is available at Aetrix Electronics and suitable for telecom infrastructure, automated test equipment, radar signal processing, and high-speed instrumentation requiring stable component supply and long-term obsolescence management.
Supply support for MC10H106FNR2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
ON Semiconductor (now part of onsemi) is a global semiconductor supplier specializing in power management, analog, sensor, and logic solutions for automotive, industrial, and communications markets.
The MC10H106FNR2 belongs to the MECL 10H family, designed specifically to replace aging MECL 10K logic with improved speed and noise immunity while preserving pinout and system integration.
FAQ
What is the recommended termination for MC10H106FNR2 outputs to meet datasheet AC specifications?
The MC10H106FNR2 outputs must be terminated with a 50 Ω resistor to −2.0 V to achieve guaranteed propagation delay and rise/fall times per Table 3. This termination matches the characteristic impedance of standard ECL transmission lines and ensures clean waveform integrity. Using alternative terminations (e.g., open-drain or unterminated) will degrade timing performance and increase jitter. Always verify termination layout symmetry across all three output groups in the MC10H106FNR2.
Does MC10H106FNR2 support operation at VEE = −5.0 V instead of the specified −5.2 V?
The MC10H106FNR2 is characterized and guaranteed only at VEE = −5.2 V ±5% (−4.94 V to −5.46 V). Operation at exactly −5.0 V falls within this range and is acceptable, but performance parameters-including VOH, VOL, and tpd-must be interpolated from the 25°C column of Tables 2 and 3. Do not operate outside the −4.94 V to −5.46 V window, as VIH/VIL thresholds and noise margin degrade unpredictably below −4.94 V.
Can MC10H106FNR2 be used in place of MC10106 in an existing design?
Yes, the MC10H106FNR2 is a functional and pinout duplication of the standard MECL 10K MC10106, with identical pin assignments (VCC1=1, VCC2=16, VEE=8) and compatible voltage thresholds. Its 100% faster propagation delay does not affect logic function, and no PCB changes are needed. However, confirm that the −5.2 V supply meets ripple and stability requirements specified for the MC10H106FNR2, as older 10K designs may use looser tolerances.
What is the maximum junction temperature for continuous operation of MC10H106FNR2?
The MC10H106FNR2 has no explicit TJ(max) rating in its datasheet, but its maximum operating ambient temperature is +75°C with ≥500 lfpm airflow. Under those conditions and 23 mA supply current, calculated junction temperature remains below 110°C using the PLLC-20 package's θJA of 50°C/W. For sealed enclosures or lower airflow, derate ambient temperature accordingly-do not exceed +65°C ambient without thermal modeling confirming TJ < 125°C.
Is MC10H106FNR2 RoHS compliant and lead-free?
Yes, the "R2" suffix in MC10H106FNR2 indicates tape-and-reel packaging, and the part is available in Pb-free version as MC10H106FNR2G (per ordering table). The base MC10H106FNR2 is not inherently lead-free; always specify the "G" suffix for RoHS-compliant shipments. ON Semiconductor confirms full compliance with EU RoHS Directive 2011/65/EU and JEDEC J-STD-609 for the G-suffix variant.
MC10H106FNR2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 10H
- Package/Case:
- 20-LCC (J-Lead)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Logic Type:
- NOR Gate
- Number of Circuits:
- 3
- Number of Inputs:
- 4, 3, 3
- Features:
- -
- Voltage - Supply:
- -4.94V ~ -5.46V
- Current - Quiescent (Max):
- -
- Current - Output High, Low:
- 50mA, 50mA
- Input Logic Level - Low:
- -1.48V
- Input Logic Level - High:
- -1.13V
- Max Propagation Delay @ V, Max CL:
- 1.5ns @ -5.2V, -
- Operating Temperature:
- 0°C ~ 75°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-PLCC (9x9)
MC10H106FNR2 FAQ
1.How can I place an order for MC10H106FNR2 through Aetrix?
Please submit a Request for Quotation (RFQ) for MC10H106FNR2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MC10H106FNR2 reliable?
The price and inventory of MC10H106FNR2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC10H106FNR2 is usually 5 days.
3.What payment methods are accepted for MC10H106FNR2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC10H106FNR2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MC10H106FNR2?
MC10H106FNR2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MC10H106FNR2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MC10H106FNR2?
For technical support, including MC10H106FNR2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC10H106FNR2 requirements.
6.How does Aetrix verify that MC10H106FNR2 is sourced from the original manufacturer or authorized distributors?
All MC10H106FNR2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC10H106FNR2 meets industry standards.
7.What is the process for return or replacement of MC10H106FNR2?
All MC10H106FNR2 units undergo pre-shipment inspection (PSI). If there is an issue with MC10H106FNR2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MC10H106FNR2 part is unused and in its original packaging.
Return procedure for MC10H106FNR2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MC10H106FNR2 Tags
-
SN74LVC1G14DBVR
Texas Instruments
-
SN74LVC1G14DCKR
Texas Instruments
-
SN74AHC1G14DBVR
Texas Instruments
-
SN74LVC1G08DBVR
Texas Instruments
-
SN74LVC1G08DCKR
Texas Instruments
-
SN74LVC1G32DCKR
Texas Instruments
-
SN74LVC1G04DBVR
Texas Instruments
.jpg)
-
74LVC1G08GW,125
Nexperia USA Inc.
-
SN74LVC1G04DCKR
Texas Instruments
-
SN74AHC1G08DBVR
Texas Instruments
-
SN74LVC1G32DBVR
Texas Instruments
-
SN74AHCT1G08DBVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

