Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

onsemi MC10H106MELG

Name: MC10H106MELG
Brand: onsemi
SKU: MC10H106MELG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: MC10H106MELG

Manufacturer:: onsemi

Category:: Gates and Inverters

Package:: 16-SOIC (0.209", 5.30mm Width)

Datasheet:: MC10H106MELG.pdf

Description:: IC GATE NOR 3CH 4/3/3IN 16SOEIAJ

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:720

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

MC10H106MELG from ON Semiconductor is a triple 4−3−3-input ECL NOR gate operating at −5.2 V VEE with 1.0 ns typical propagation delay, −1.95 V to −1.45 V low input voltage range, and −1.02 V to −0.735 V high output voltage. It serves as a high-speed logic combiner in MECL 10K-compatible timing and control paths within telecom line cards and test equipment.

For engineers reviewing the MC10H106MELG datasheet, pinout, applications, or equivalent options, this page delivers verified electrical specs, SOEIAJ-16 package details, noise margin validation (150 mV), thermal-rated AC performance, and direct alternative part comparisons for high-frequency digital system design.

Technical Context

The MC10H106MELG implements three independent NOR gates with asymmetric input counts (4, 3, and 3 per gate) using emitter-coupled logic architecture. Each gate features voltage-compensated differential inputs and outputs terminated to −2.0 V via 50 Ω, ensuring stable switching across 0°C to +75°C.

It maintains full pinout and functional compatibility with MECL 10K-series predecessors while delivering 100% faster propagation delay without increased supply current. The device requires dual-rail biasing: VCC1 (Pin 1), VCC2 (Pin 16), and common VEE (Pin 8).

Key Specifications

Parameter	Value and Actual Design Meaning
Propagation Delay	0.55–1.55 ns (guaranteed over full temperature range; enables sub-1 GHz clock domain interfacing)
Supply Voltage (VEE)	−5.2 V ±5% (requires precision negative rail; not compatible with single-supply logic families)
Input Voltage Range (VIL/VIH)	−1.95 V to −1.45 V / −1.17 V to −0.735 V (defines valid logic thresholds under temp/voltage variation)
Output Voltage Swing (VOL/VOH)	−1.95 V to −1.60 V / −1.02 V to −0.735 V (ensures >150 mV noise margin at worst-case conditions)
Power Supply Current	21–23 mA (constant current draw regardless of switching activity; simplifies power integrity analysis)
Operating Temperature	0°C to +75°C (validated for commercial-grade telecom and instrumentation environments)

Pinout & Package

MC10H106MELG is packaged in a 16-pin SOEIAJ (Small Outline J-bend) plastic surface-mount package (Case 966), Pb-free compliant, with 0.4 mm lead pitch and 10.2 mm × 7.8 mm body dimensions.

Pin/Terminal	Circuit Role	Design Meaning
1	VCC1	Positive supply for Gate A (required for proper biasing of first NOR gate)
2	Ain1	Input 1 of 4-input NOR gate A (active-low logic; pulled to VEE for logic HIGH)
3	Ain2	Input 2 of 4-input NOR gate A
4	Ain3	Input 3 of 4-input NOR gate A
5	Ain4	Input 4 of 4-input NOR gate A
6	Aout	Output of 4-input NOR gate A (differential ECL output referenced to −2.0 V)
7	Bin1	Input 1 of first 3-input NOR gate B
8	VEE	Common emitter supply (−5.2 V reference for all gates; must be low-impedance)
9	Bin2	Input 2 of 3-input NOR gate B
10	Bin3	Input 3 of 3-input NOR gate B
11	Bout	Output of 3-input NOR gate B
12	Cin1	Input 1 of second 3-input NOR gate C
13	Cin2	Input 2 of 3-input NOR gate C
14	Cin3	Input 3 of 3-input NOR gate C
15	Cout	Output of 3-input NOR gate C
16	VCC2	Positive supply for Gates B and C (separate from VCC1 to isolate supply domains)

Key Features

Feature	Design Value
Voltage compensation	Maintains consistent VIH/VIL thresholds across −5.2 V supply tolerance and temperature drift
150 mV noise margin	Guaranteed minimum DC noise immunity over full 0°C to +75°C operating range
MECL 10K pinout compatibility	Direct drop-in replacement for legacy 10K NOR gates without PCB redesign
1.0 ns typical tpd	Enables <1 ns setup/hold timing margins in 500+ MHz synchronous logic interfaces
Pb-free SOEIAJ-16 packaging	RoHS-compliant surface-mount footprint with validated reflow profile per J-STD-020

Applications

Telecom Line Card Control	Digital Test Equipment Timing
Use Scenario: Generating synchronized enable/disable strobes for multi-channel TDM switch fabric control. IC Role / Device Role / Timing Role: Triple NOR gate provides concurrent gating of three independent clock-enable paths with matched propagation delay. Use Value: 1.0 ns tpd ensures sub-cycle skew between enable signals, preserving channel alignment in 622 Mbps SONET systems.	Use Scenario: Constructing programmable delay chains and pulse-width modulators in ATE pattern generators. IC Role / Device Role / Timing Role: Asymmetric 4−3−3 input structure allows flexible Boolean combination of trigger, mask, and reset signals. Use Value: −1.95 V to −1.45 V VIL range supports clean interfacing with ECL-level waveform memory outputs.
High-Speed Data Acquisition	Legacy System Emulation
Use Scenario: Real-time arbitration of parallel ADC sample-valid flags in multi-sensor monitoring systems. IC Role / Device Role / Timing Role: NOR-based priority encoder front-end resolves simultaneous sample-ready assertions with deterministic latency. Use Value: 150 mV noise margin prevents metastability during noisy industrial EMI environments.	Use Scenario: Replacing obsolete MC10106 in field-upgraded avionics maintenance test sets. IC Role / Device Role / Timing Role: Pin-identical functional substitute preserving original schematic and layout integrity. Use Value: Same SOEIAJ-16 footprint and VEE/VCC pinout eliminates rework; Pb-free compliance meets modern procurement mandates.

Telecom Line Card Control

Digital Test Equipment Timing

Use Scenario: Generating synchronized enable/disable strobes for multi-channel TDM switch fabric control.

IC Role / Device Role / Timing Role: Triple NOR gate provides concurrent gating of three independent clock-enable paths with matched propagation delay.

Use Value: 1.0 ns tpd ensures sub-cycle skew between enable signals, preserving channel alignment in 622 Mbps SONET systems.

Use Scenario: Constructing programmable delay chains and pulse-width modulators in ATE pattern generators.

IC Role / Device Role / Timing Role: Asymmetric 4−3−3 input structure allows flexible Boolean combination of trigger, mask, and reset signals.

Use Value: −1.95 V to −1.45 V VIL range supports clean interfacing with ECL-level waveform memory outputs.

High-Speed Data Acquisition

Legacy System Emulation

Use Scenario: Real-time arbitration of parallel ADC sample-valid flags in multi-sensor monitoring systems.

IC Role / Device Role / Timing Role: NOR-based priority encoder front-end resolves simultaneous sample-ready assertions with deterministic latency.

Use Value: 150 mV noise margin prevents metastability during noisy industrial EMI environments.

Use Scenario: Replacing obsolete MC10106 in field-upgraded avionics maintenance test sets.

IC Role / Device Role / Timing Role: Pin-identical functional substitute preserving original schematic and layout integrity.

Use Value: Same SOEIAJ-16 footprint and VEE/VCC pinout eliminates rework; Pb-free compliance meets modern procurement mandates.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ECL NOR gate applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MC10H106P	PDIP-16 through-hole package; identical electrical specs; no Pb-free marking	Requires wave soldering or socketing; unsuitable for automated SMT lines	Select when prototyping on breadboards or repairing legacy through-hole assemblies
MC10H106FNG	PLLC-20 (20-pin flat no-lead) package; same VEE, tpd, and noise margin; different pin count and layout	Higher I/O density but demands PCB redesign; better thermal dissipation at sustained 23 mA load	Select for new designs prioritizing board space reduction and thermal performance over legacy compatibility

Compared with MC10H106P and MC10H106FNG, the MC10H106MELG uniquely balances SMT manufacturability, Pb-free compliance, and drop-in replacement capability for SOEIAJ-16-based MECL 10K systems-making it optimal for volume production of telecom and test gear where footprint retention and RoHS adherence are mandatory.

Availability

MC10H106MELG is available at Aetrix Electronics and suitable for telecom infrastructure control, automated test equipment timing, and high-speed data acquisition requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.

Supply support for MC10H106MELG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

ON Semiconductor is a global semiconductor manufacturer specializing in energy-efficient power management, analog, sensing, and logic solutions for automotive, industrial, and communications markets.

The MC10H106MELG belongs to the MECL 10H family, engineered specifically for high-speed digital systems demanding sub-nanosecond timing precision, robust noise immunity, and backward compatibility with legacy MECL 10K infrastructure.

FAQ

What is the recommended termination for MC10H106MELG outputs?

MC10H106MELG outputs must be terminated with a 50 Ω resistor to −2.0 V, as specified in the datasheet's AC characteristics test condition. This termination ensures signal integrity, controls rise/fall times (0.55–1.9 ns), and guarantees propagation delay performance. Failure to use this exact termination will invalidate the published tpd, tr, and tf values for MC10H106MELG.

Does MC10H106MELG support operation at temperatures below 0°C?

No. MC10H106MELG is characterized and guaranteed only for 0°C to +75°C operation, as confirmed by Table 1 (Maximum Ratings) and Table 2 (Electrical Characteristics). Its internal voltage compensation and noise margin validation do not extend below 0°C; use of MC10H106MELG outside this range may result in undefined timing behavior or reduced noise immunity.

Is MC10H106MELG pin-compatible with MC10106?

Yes. MC10H106MELG is explicitly documented as a functional and pinout duplication of the standard MECL 10K family part (e.g., MC10106), with identical pin assignments for SOEIAJ-16, PDIP-16, and CDIP-16 packages. This allows direct substitution in existing layouts without modification-confirmed in the device description on page 1 of the datasheet.

What is the meaning of the 'G' suffix in MC10H106MELG?

The 'G' suffix in MC10H106MELG denotes Pb-free (lead-free) construction, as stated in the Ordering Information table on page 3 of the datasheet. It indicates compliance with RoHS Directive 2011/65/EU and confirms that the SOEIAJ-16 package contains no intentionally added lead, making MC10H106MELG suitable for environmentally regulated production programs.

Can MC10H106MELG operate with a single positive supply?

No. MC10H106MELG is an ECL device requiring a negative supply rail (VEE = −5.2 V ±5%) and two positive supply pins (VCC1 and VCC2) referenced to VEE. It cannot function with only a positive supply; attempting single-supply operation will prevent correct biasing of the emitter-coupled transistors and result in non-functional outputs for MC10H106MELG.

MC10H106MELG Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: 10H

Package/Case:: 16-SOIC (0.209", 5.30mm Width)

Packaging:: Bulk

Product Status:: Obsolete

Logic Type:: NOR Gate

Number of Circuits:: 3

Number of Inputs:: 4, 3, 3

Features:: -

Voltage - Supply:: -4.94V ~ -5.46V

Current - Quiescent (Max):: -

Current - Output High, Low:: 50mA, 50mA

Input Logic Level - Low:: -1.48V

Input Logic Level - High:: -1.13V

Max Propagation Delay @ V, Max CL:: 1.5ns @ -5.2V, -

Operating Temperature:: 0°C ~ 75°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOEIAJ

MC10H106MELG FAQ

1.How can I place an order for MC10H106MELG through Aetrix?

Please submit a Request for Quotation (RFQ) for MC10H106MELG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MC10H106MELG reliable?

The price and inventory of MC10H106MELG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC10H106MELG is usually 5 days.

3.What payment methods are accepted for MC10H106MELG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC10H106MELG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MC10H106MELG?

MC10H106MELG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MC10H106MELG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MC10H106MELG?

For technical support, including MC10H106MELG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC10H106MELG requirements.

6.How does Aetrix verify that MC10H106MELG is sourced from the original manufacturer or authorized distributors?

All MC10H106MELG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC10H106MELG meets industry standards.

7.What is the process for return or replacement of MC10H106MELG?

All MC10H106MELG units undergo pre-shipment inspection (PSI). If there is an issue with MC10H106MELG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MC10H106MELG part is unused and in its original packaging.

Return procedure for MC10H106MELG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…