onsemi MC10H106MG
- Part No.:
- MC10H106MG
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 16-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
MC10H106MG.pdf
- Description:
- IC GATE NOR 3CH 4/3/3IN 16SOEIAJ
- Quantity:
- Payment:

- Shipping:

Inventory:5,200
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MC10H106MG from ON Semiconductor is a triple 4−3−3-input ECL NOR gate operating at −5.2 V VEE with 1.0 ns typical propagation delay, −1.95 V to −1.60 V low-output voltage range, and MECL 10K pinout compatibility. It serves as high-speed logic combiner in clock distribution, data path steering, and bus arbitration circuits within telecom line cards and test equipment.
For engineers reviewing the MC10H106MG datasheet, pinout, applications, or equivalent options, this page delivers verified electrical specs, SOEIAJ-16 package details, thermal-rated AC performance across 0°C–75°C, and two validated alternative parts for ECL logic replacement scenarios.
Technical Context
The MC10H106MG implements three independent NOR gates with asymmetric input counts (four inputs on Gate A, three each on Gates B and C), all sharing common VCC1, VCC2, and VEE supply rails. Its ECL topology ensures differential switching with voltage-compensated biasing for stable operation over temperature.
Each gate drives into 50 Ω terminated to −2.0 V, meeting MECL 10K timing and voltage thresholds while delivering 100% faster propagation than legacy 10K equivalents. Input current ranges from +0.5 µA (low) to −310 µA (high), supporting wired-OR interconnects without external pull-downs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Propagation Delay | 0.55–1.55 ns (measured at 25°C–75°C, enables sub-1 GHz combinational logic paths) |
| Supply Voltage (VEE) | −5.2 V ±5% (requires negative rail regulation; VCC1/VCC2 = 0 V reference) |
| Output Voltage (VOL) | −1.95 V to −1.60 V (ensures >150 mV noise margin against adjacent ECL signals) |
| Input Current (IinL) | +0.3 to +0.5 µA (enables direct connection to TTL/CMOS outputs via level-shifting resistors) |
| Operating Temp | 0°C to +75°C (validated for commercial-grade telecom and instrumentation environments) |
| Power Supply Current | 21–23 mA (constant-current ECL core; no dynamic power scaling) |
Pinout & Package
MC10H106MG uses a 16-pin SOEIAJ surface-mount package (Case 966), 10.5 mm × 7.6 mm footprint, 1.7 mm max height, Pb-free lead finish. Pin 1 is VCC1; Pin 16 is VCC2; Pin 8 is VEE.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 16 | VCC1 / VCC2 | Logic ground reference for internal emitter followers; must be tied to 0 V |
| 8 | VEE | Negative supply rail (−5.2 V); sets logic threshold and output swing |
| 2, 3, 4, 5 | Ain1–Ain4 | Four-input NOR gate A inputs; active-high logic per ECL convention |
| 6, 7, 15 | Bin1–Bin3 | Three-input NOR gate B inputs; compatible with standard MECL 10K wiring |
| 9, 10, 11 | Cin1–Cin3 | Three-input NOR gate C inputs; electrically isolated from other gates |
| 12, 13, 14 | Aout, Bout, Cout | Complemented NOR outputs; drive 50 Ω to −2.0 V for impedance-matched transmission |
Key Features
| Feature | Design Value |
|---|---|
| 1.0 ns typical propagation delay | Enables <1 ns critical path timing in multi-gate ECL data selectors and synchronizers |
| 150 mV noise margin | Guaranteed across full temperature range, eliminating need for guard bands in dense PCB layouts |
| MECL 10K pinout compatibility | Direct drop-in replacement for MC10106/MC10107 in existing 10K designs without layout change |
| Voltage-compensated biasing | Maintains consistent switching thresholds despite VEE drift or temperature variation |
| Pb-free SOEIAJ-16 package | RoHS-compliant surface-mount solution with 0.65 mm lead pitch for automated assembly |
Applications
| Telecom Line Card Timing | Digital Test Equipment Signal Routing |
|---|---|
|
Use Scenario: Synchronizing multiple DS3/E3 framers with phase-aligned enable signals. IC Role / Device Role / Timing Role: NOR gate A combines frame sync and reset pulses to generate glitch-free strobes. Use Value: 1.0 ns propagation ensures sub-cycle alignment across 48 MHz framers without added skew compensation. |
Use Scenario: Dynamic reconfiguration of stimulus paths in high-speed pattern generators. IC Role / Device Role / Timing Role: Gate B selects between two parallel data buses using address bits and chip-enable. Use Value: −1.95 V to −1.60 V VOL range maintains signal integrity into 50 Ω scope inputs and logic analyzers. |
| High-Speed Bus Arbitration | RF Transceiver Control Logic |
|
Use Scenario: Resolving simultaneous access requests from four DSP cores sharing a shared memory bus. IC Role / Device Role / Timing Role: Gate C computes priority-encoded grant signals from request lines. Use Value: 150 mV noise margin prevents false grants in electrically noisy multi-core backplanes. |
Use Scenario: Generating synchronized TX/RX enable and PA bias control in 2G/3G baseband modules. IC Role / Device Role / Timing Role: NOR gate A combines PLL lock status and mode select to gate RF power-up sequence. Use Value: Voltage-compensated biasing ensures reliable startup across −40°C to +85°C extended temp variants. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ECL NOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC10H106M | Same die, SnPb lead finish; 21–23 mA supply current identical | Not RoHS-compliant; requires exemption documentation for EU/China shipments | Select MC10H106M only if legacy Pb-based solder process is mandated and compliance waivers apply. |
| MC100H106FN | PLLC-20 package (20-pin), −4.5 V to −5.5 V VEE range, 0.45 ns faster tpd | Requires PCB redesign due to different pin count, pitch, and thermal pad layout | Choose MC100H106FN when sub-1 ns timing is mandatory and board revision is feasible. |
Compared with MC10H106M, the MC10H106MG offers identical speed and logic function with RoHS compliance; versus MC100H106FN, it trades 0.45 ns speed gain for SOEIAJ-16 drop-in fit and lower thermal resistance in compact layouts.
Availability
MC10H106MG is available at Aetrix Electronics and suitable for telecom infrastructure, automated test equipment, and industrial control systems requiring stable component supply with guaranteed long-term sourcing.
Supply support for MC10H106MG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
ON Semiconductor is a global semiconductor supplier delivering energy-efficient, high-performance silicon solutions for automotive, industrial, cloud computing, and communications markets.
The MC10H106MG belongs to the MECL 10H family-designed for high-speed digital systems where deterministic timing, noise immunity, and backward compatibility with 10K logic are essential.
FAQ
What is the recommended termination for MC10H106MG outputs?
MC10H106MG outputs must be terminated with a 50 Ω resistor to −2.0 V, as specified in the datasheet's AC characteristics test conditions. This termination ensures proper signal integrity, meets rise/fall time specs (0.55–1.9 ns), and maintains the 150 mV noise margin. Using unmatched or open-circuit loads will degrade propagation delay and increase jitter in high-speed paths.
Does MC10H106MG support mixed-voltage interfacing with TTL or CMOS devices?
MC10H106MG can interface with TTL or CMOS inputs using resistor-based level shifting: a pull-up resistor from MC10H106MG output to 0 V converts its negative ECL swing (−1.95 V to −0.735 V) to positive logic levels acceptable to 5 V TTL. Direct connection is not possible due to incompatible voltage domains and current-sinking input structure.
Is MC10H106MG pin-compatible with the original MECL 10K MC10106?
Yes, MC10H106MG is a functional and pinout duplication of the MECL 10K MC10106, as confirmed in the device description. All 16 pins map identically-including VCC1 (Pin 1), VEE (Pin 8), VCC2 (Pin 16), and all input/output assignments-enabling drop-in replacement without PCB modification.
What is the maximum junction temperature for continuous operation of MC10H106MG?
The MC10H106MG has no explicit TJ(max) rating in its datasheet, but its operating temperature range is specified as 0°C to +75°C ambient. With SOEIAJ-16 thermal resistance (θJA ≈ 120°C/W), sustained 23 mA supply current yields ~280 mW dissipation, limiting safe continuous operation to ≤+75°C ambient under still-air conditions per standard JEDEC testing.
Can MC10H106MG be used in systems requiring extended temperature range beyond 0°C to +75°C?
No-MC10H106MG is characterized and guaranteed only for 0°C to +75°C ambient operation. The datasheet does not specify parameters or reliability data outside this range. For extended temperature use, consider the MC100H106 series (−40°C to +85°C), which shares logic function but differs in package and pinout.
MC10H106MG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 10H
- Package/Case:
- 16-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- NOR Gate
- Number of Circuits:
- 3
- Number of Inputs:
- 4, 3, 3
- Features:
- -
- Voltage - Supply:
- -4.94V ~ -5.46V
- Current - Quiescent (Max):
- -
- Current - Output High, Low:
- 50mA, 50mA
- Input Logic Level - Low:
- -1.48V
- Input Logic Level - High:
- -1.13V
- Max Propagation Delay @ V, Max CL:
- 1.5ns @ -5.2V, -
- Operating Temperature:
- 0°C ~ 75°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOEIAJ
MC10H106MG FAQ
1.How can I place an order for MC10H106MG through Aetrix?
Please submit a Request for Quotation (RFQ) for MC10H106MG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MC10H106MG reliable?
The price and inventory of MC10H106MG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC10H106MG is usually 5 days.
3.What payment methods are accepted for MC10H106MG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC10H106MG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MC10H106MG?
MC10H106MG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MC10H106MG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MC10H106MG?
For technical support, including MC10H106MG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC10H106MG requirements.
6.How does Aetrix verify that MC10H106MG is sourced from the original manufacturer or authorized distributors?
All MC10H106MG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC10H106MG meets industry standards.
7.What is the process for return or replacement of MC10H106MG?
All MC10H106MG units undergo pre-shipment inspection (PSI). If there is an issue with MC10H106MG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MC10H106MG part is unused and in its original packaging.
Return procedure for MC10H106MG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MC10H106MG Tags
-
SN74LVC1G14DBVR
Texas Instruments
-
SN74LVC1G14DCKR
Texas Instruments
-
SN74AHC1G14DBVR
Texas Instruments
-
SN74LVC1G08DBVR
Texas Instruments
-
SN74LVC1G08DCKR
Texas Instruments
-
SN74LVC1G32DCKR
Texas Instruments
-
SN74LVC1G04DBVR
Texas Instruments
.jpg)
-
74LVC1G08GW,125
Nexperia USA Inc.
-
SN74LVC1G04DCKR
Texas Instruments
-
SN74AHC1G08DBVR
Texas Instruments
-
SN74LVC1G32DBVR
Texas Instruments
-
SN74AHCT1G08DBVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

