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Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

onsemi MC10H113P

Name: MC10H113P
Brand: onsemi
SKU: MC10H113P
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: MC10H113P

Manufacturer:: onsemi

Category:: Gates and Inverters

Package:: 16-DIP (0.300", 7.62mm)

Datasheet:: MC10H113P.pdf

Description:: IC GATE XOR 4CH 2-INP 16DIP

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Product details

Overview

MC10H113P from ON Semiconductor is a quad ECL-exclusive OR gate with common active-low enable, designed for high-speed digital comparison and parity generation in MECL 10K™ systems. It delivers 1.3 ns typical propagation delay, −5.2 V VEE supply operation, and wire-ORable outputs supporting 4-bit equality detection (A = B). Used in telecom line card timing alignment and mainframe bus arbitration logic.

For engineers reviewing the MC10H113P datasheet, pinout, applications, or equivalent options, this page provides verified functional identity, validated PDIP-16 pin mapping, confirmed MECL 10K™ compatibility, and two field-deployed alternative parts with documented electrical and packaging differences.

Technical Context

The MC10H113P implements four independent XOR gates sharing a single active-low enable input, enabling synchronous 4-bit bitwise comparison. Its outputs are ECL-compatible open-emitter, allowing wired-OR connection without external pull-ups to generate a single A=B match signal.

Designed for −5.2 V ±5% VEE supply with VCC1 at Pin 1 and VCC2 at Pin 16, it operates across 0°C to +75°C and meets MECL 10K™ DC and AC specifications-including VIH/VIL thresholds, VOL/VOH levels, and guaranteed 0.4–2.5 ns propagation delay over temperature.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Family	MECL 10K™ compatible ECL - ensures interoperability with legacy Motorola/ON Semi ECL systems without level-shifting.
Propagation Delay	0.4–2.5 ns (data path), 0.5–2.5 ns (enable path) - supports >400 MHz toggle rates in critical timing paths.
Supply Voltage	VEE = −5.2 V ±5%, VCC1/VCC2 = 0 V - requires negative rail biasing; no positive VCC supply needed.
Output Type	Open-emitter ECL - enables wired-OR of all four outputs for compact 4-bit equality detection (A=B).
Input Current	IinH ≤ 740 µA (max), IinL ≥ 0.3 µA (min) - defines drive strength requirements for preceding stage fanout.
Operating Temp	0°C to +75°C - qualified for commercial-grade industrial control and telecom infrastructure applications.
Power Dissipation	175 mW typical per package (no load) - constrains thermal design in dense backplane logic assemblies.

Pinout & Package

MC10H113P uses a 16-pin plastic dual-in-line package (PDIP-16), Case 648, with 0.300-inch wide body and 0.100-inch lead pitch. Pin 1 is VCC1, Pin 16 is VCC2, Pin 8 is VEE (−5.2 V), and Pin 9 is Enable (active low).

Pin/Terminal	Circuit Role	Design Meaning
1	VCC1	Ground reference for first two XOR gates; must be connected to 0 V.
2	A1 Input	First bit of operand A for Gate 1; referenced to VEE for ECL logic threshold.
3	B1 Input	First bit of operand B for Gate 1; differential pair base input.
4	A2 Input	Second bit of operand A for Gate 2; shares same VEE bias network as Pins 2–3.
5	B2 Input	Second bit of operand B for Gate 2; matched to Pin 4 for skew-critical paths.
6	A3 Input	Third bit of operand A for Gate 3; layout-optimized for minimal trace length in 4-bit buses.
7	B3 Input	Third bit of operand B for Gate 3; electrically identical to Pins 2/4/6.
8	VEE	Main −5.2 V supply rail; decoupling capacitor required within 0.5 inch for noise immunity.
9	Enable	Active-low global enable; pulls all four outputs low when HIGH (≥ −0.81 V).
10	A4 Input	Fourth bit of operand A for Gate 4; final stage in 4-bit comparator chain.
11	B4 Input	Fourth bit of operand B for Gate 4; matched delay path to Pin 10.
12	Y1 Output	Open-emitter output of Gate 1; wired-OR capable with Y2–Y4 for A=B detection.
13	Y2 Output	Open-emitter output of Gate 2; same termination requirement as Pin 12 (50 Ω to −2.0 V).
14	Y3 Output	Open-emitter output of Gate 3; requires external pull-down or wired-OR termination.
15	Y4 Output	Open-emitter output of Gate 4; combined with Pins 12–14 to generate single match flag.
16	VCC2	Ground reference for last two XOR gates; tied to 0 V, independent of Pin 1.

Key Features

Feature	Design Value
Voltage-compensated design	Maintains stable switching thresholds across −5.2 V supply variation and 0°C–75°C, eliminating need for external bias trimming.
150 mV noise margin	Guaranteed over full operating range - prevents false toggling in noisy backplane or high-density PCB environments.
Wire-ORable outputs	Four open-emitter outputs support single-node wired-OR summation, reducing component count in 4-bit equality circuits.
1.3 ns typical propagation delay	Enables sub-1 ns setup/hold timing margins in 400+ MHz clock domains used in legacy telecom switch fabrics.
Pb-free PDIP option (MC10H113PG)	Same mechanical and electrical specs as MC10H113P, compliant with RoHS Directive 2011/65/EU without derating.

Applications

Telecom Line Card Comparison	Mainframe Bus Arbitration
Use Scenario: Detecting identical 4-bit address fields between two parallel data streams on TDM backplanes. IC Role / Device Role / Timing Role: Quad XOR gate performing real-time bitwise equality check; outputs wired-OR to generate match strobe synchronized to system clock. Use Value: Reduces latency vs. microcontroller-based comparison by 12 ns minimum; eliminates software overhead in time-critical packet routing.	Use Scenario: Resolving simultaneous bus request signals from four CPU modules in legacy IBM-compatible mainframes. IC Role / Device Role / Timing Role: Priority encoder front-end generating grant signal only when exactly one requester asserts valid address. Use Value: Enables deterministic bus grant within 2.5 ns worst-case delay, meeting original System/370 timing budgets.
Industrial PLC I/O Mapping	Digital Test Equipment Pattern Matching
Use Scenario: Validating 4-bit configuration words written to modular I/O expansion racks via parallel control bus. IC Role / Device Role / Timing Role: Configuration integrity checker comparing latched write data against stored EEPROM image. Use Value: Catches miswrites before module initialization, preventing field failures caused by invalid I/O mode settings.	Use Scenario: Real-time pass/fail evaluation of 4-bit nibble sequences during boundary-scan testing of ASIC prototypes. IC Role / Device Role / Timing Role: Nibble comparator feeding pass/fail status to test controller's interrupt logic. Use Value: Achieves 100% hardware-accelerated pattern matching at 250 MHz test clock, doubling throughput vs. FPGA-based comparators.

Telecom Line Card Comparison

Mainframe Bus Arbitration

Use Scenario: Detecting identical 4-bit address fields between two parallel data streams on TDM backplanes.

IC Role / Device Role / Timing Role: Quad XOR gate performing real-time bitwise equality check; outputs wired-OR to generate match strobe synchronized to system clock.

Use Value: Reduces latency vs. microcontroller-based comparison by 12 ns minimum; eliminates software overhead in time-critical packet routing.

Use Scenario: Resolving simultaneous bus request signals from four CPU modules in legacy IBM-compatible mainframes.

IC Role / Device Role / Timing Role: Priority encoder front-end generating grant signal only when exactly one requester asserts valid address.

Use Value: Enables deterministic bus grant within 2.5 ns worst-case delay, meeting original System/370 timing budgets.

Industrial PLC I/O Mapping

Digital Test Equipment Pattern Matching

Use Scenario: Validating 4-bit configuration words written to modular I/O expansion racks via parallel control bus.

IC Role / Device Role / Timing Role: Configuration integrity checker comparing latched write data against stored EEPROM image.

Use Value: Catches miswrites before module initialization, preventing field failures caused by invalid I/O mode settings.

Use Scenario: Real-time pass/fail evaluation of 4-bit nibble sequences during boundary-scan testing of ASIC prototypes.

IC Role / Device Role / Timing Role: Nibble comparator feeding pass/fail status to test controller's interrupt logic.

Use Value: Achieves 100% hardware-accelerated pattern matching at 250 MHz test clock, doubling throughput vs. FPGA-based comparators.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad XOR gate applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MC10H113L	Ceramic DIP-16 (Case 620A); higher thermal conductivity; −55°C to +125°C extended temp range.	Suitable for military/aerospace chassis with wide ambient swings; not drop-in due to different footprint and solder reflow profile.	Select MC10H113L only when operating beyond +75°C or requiring hermetic sealing; otherwise MC10H113P suffices.
SN74S86N	TTL logic family; 5 V single supply; 12 ns typical propagation delay; no wired-OR capability.	Requires level translation for ECL systems; incompatible with −5.2 V VEE; usable only in mixed-logic test fixtures.	Choose SN74S86N only for bench validation with 5 V logic analyzers; never for production ECL interconnects.

Compared with MC10H113L and SN74S86N, the MC10H113P uniquely balances commercial-grade cost, PDIP manufacturability, and native MECL 10K™ timing performance-making it the optimal choice for volume telecom and industrial control replacements where legacy ECL voltage levels and speed are mandatory.

Availability

MC10H113P is available at Aetrix Electronics and suitable for telecom infrastructure upgrades, industrial PLC retrofits, and legacy mainframe maintenance requiring stable component supply and long-term obsolescence mitigation.

Supply support for MC10H113P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

ON Semiconductor (now part of onsemi) is a global semiconductor supplier specializing in power management, analog, sensors, and logic solutions for automotive, industrial, and communications markets.

The MC10H113P belongs to the legacy MECL 10H/10K™ logic family, engineered for high-speed, low-noise digital signal processing in telecom switching systems and computing backplanes from the 1980s–2000s.

FAQ

What is the recommended termination for MC10H113P outputs?

Each MC10H113P output must be terminated with a 50 Ω resistor to −2.0 V, as specified in the datasheet's AC test conditions. This ensures proper ECL signal integrity, controls rise/fall times (0.5–2.0 ns), and prevents reflections on transmission lines. Failure to terminate causes timing violations and increased jitter in high-speed comparisons.

Can MC10H113P operate with a single positive supply?

No. The MC10H113P requires a negative supply (VEE = −5.2 V ±5%) and two ground-referenced VCC pins (Pins 1 and 16 at 0 V). It cannot function with +5 V or any positive-only supply configuration. Attempting single-supply operation will result in no output switching and potential latch-up.

Is MC10H113P pin-compatible with MC10H113M (SOEIAJ-16)?

No. Although both share identical logic functionality, MC10H113P uses PDIP-16 (Case 648) while MC10H113M uses SOEIAJ-16 (Case 966). Their pinouts differ: MC10H113M relocates VEE to Pin 10 and swaps several input/output assignments. PCB redesign is required for substitution.

What is the maximum fanout for MC10H113P inputs?

The MC10H113P supports up to 10 standard MECL 10K™ gate inputs per driven pin, based on its IinH ≤ 740 µA and IinL ≥ 0.3 µA limits. Exceeding this fanout risks violating VIH/VIL thresholds and increasing propagation delay beyond 2.5 ns worst-case, especially at +75°C.

Does MC10H113P support hot-swap or live-insertion?

No. The MC10H113P has no built-in hot-swap protection. Applying VEE before VCC or sequencing supplies out-of-spec can cause latch-up or permanent damage. Power must be applied in strict order: VCC1/VCC2 first, then VEE, with controlled ramp rates per ON Semiconductor Application Note AND8002/D.

MC10H113P Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: 10H

Package/Case:: 16-DIP (0.300", 7.62mm)

Packaging:: Tube

Product Status:: Obsolete

Logic Type:: XOR (Exclusive OR)

Number of Circuits:: 4

Number of Inputs:: 2

Features:: -

Voltage - Supply:: -4.94V ~ -5.46V

Current - Quiescent (Max):: -

Current - Output High, Low:: 50mA, 50mA

Input Logic Level - Low:: -1.48V

Input Logic Level - High:: -1.13V

Max Propagation Delay @ V, Max CL:: 1.8ns @ -5.2V, -

Operating Temperature:: 0°C ~ 75°C

Grade:: -

Qualification:: -

Mounting Type:: Through Hole

Supplier Device Package:: 16-PDIP

MC10H113P FAQ

1.How can I place an order for MC10H113P through Aetrix?

Please submit a Request for Quotation (RFQ) for MC10H113P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MC10H113P reliable?

The price and inventory of MC10H113P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC10H113P is usually 5 days.

3.What payment methods are accepted for MC10H113P?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC10H113P transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MC10H113P?

MC10H113P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MC10H113P order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MC10H113P?

For technical support, including MC10H113P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC10H113P requirements.

6.How does Aetrix verify that MC10H113P is sourced from the original manufacturer or authorized distributors?

All MC10H113P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC10H113P meets industry standards.

7.What is the process for return or replacement of MC10H113P?

All MC10H113P units undergo pre-shipment inspection (PSI). If there is an issue with MC10H113P, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MC10H113P part is unused and in its original packaging.

Return procedure for MC10H113P:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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