onsemi MC10H113PG
- Part No.:
- MC10H113PG
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
MC10H113PG.pdf
- Description:
- IC GATE XOR 4CH 2-INP 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:248
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Product details
Overview
MC10H113PG from ON Semiconductor is a quad ECL-exclusive OR gate with a common active-low enable input, designed for high-speed digital comparison and arithmetic logic in MECL 10K-compatible systems. It delivers 1.3 ns typical propagation delay, −5.2 V VEE operation, and supports wire-ORed outputs for 4-bit equality detection (A = B). Used in telecom line card timing alignment and legacy mainframe bus arbitration.
For engineers reviewing the MC10H113PG datasheet, pinout, applications, or equivalent options, this page provides verified electrical specs, package mapping to PDIP-16, wire-OR capability confirmation, thermal derating data across 0–75°C, and validated alternatives for ECL logic replacement.
Technical Context
The MC10H113PG implements four independent XOR gates sharing a single active-low enable (Pin 9), with all inputs and outputs referenced to VEE (−5.2 V) and dual VCC supplies (Pins 1 and 16). Its ECL topology ensures differential noise immunity and sub-2 ns transition times.
Outputs are open-emitter compatible for wired-OR summation-enabling direct 4-bit equality comparison without external logic. The device meets MECL 10K voltage thresholds (VIH = −1.17 V min, VIL = −1.95 V max at 25°C) and operates within 0°C to +75°C ambient range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | MECL 10H, fully compatible with MECL 10K systems |
| Propagation Delay | 1.3 ns typical (data path), 2.3 ns max (enable path) at 25°C |
| Supply Voltage | VEE = −5.2 V ±5%; VCC1/Pin 1 & VCC2/Pin 16 = 0 V reference |
| Output Type | Open-emitter, wire-OR capable for A=B comparison function |
| Operating Temperature | 0°C to +75°C - validated performance across full range per Table 2/3 |
| Power Dissipation | 175 mW typical per package (no load), scalable with fan-out |
| Input Voltage Range | VIH = −1.17 V min, VIL = −1.95 V max at 25°C - defines noise margin |
Pinout & Package
MC10H113PG is supplied in a Pb-free plastic dual-in-line package (PDIP-16), Case 648, with 0.300-inch body width and standard through-hole mounting. Pin 1 is VCC1; Pin 16 is VCC2; Pin 8 is VEE (−5.2 V); Pin 9 is active-low Enable.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | VCC1 | First VCC reference node (0 V) for Gates 1 & 2 |
| 2 | A1 Input | First input of Gate 1 (XOR A1⊕B1) |
| 3 | B1 Input | Second input of Gate 1 |
| 4 | A2 Input | First input of Gate 2 (XOR A2⊕B2) |
| 5 | B2 Input | Second input of Gate 2 |
| 6 | A3 Input | First input of Gate 3 (XOR A3⊕B3) |
| 7 | B3 Input | Second input of Gate 3 |
| 8 | VEE | Common emitter supply (−5.2 V) |
| 9 | Enable (Active Low) | Global gate enable - all outputs high-Z when HIGH |
| 10 | A4 Input | First input of Gate 4 (XOR A4⊕B4) |
| 11 | B4 Input | Second input of Gate 4 |
| 12 | Y1 Output | Open-emitter output of Gate 1 - requires pull-up to VCC |
| 13 | Y2 Output | Open-emitter output of Gate 2 |
| 14 | Y3 Output | Open-emitter output of Gate 3 |
| 15 | Y4 Output | Open-emitter output of Gate 4 |
| 16 | VCC2 | Second VCC reference node (0 V) for Gates 3 & 4 |
Key Features
| Feature | Design Value |
|---|---|
| Propagation Delay | 1.3 ns typical enables <770 MHz toggle rate in feedback loops |
| Noise Margin | 150 mV guaranteed over full temp/voltage range - critical for backplane signal integrity |
| Wire-OR Capability | Open-emitter outputs allow hardware-level 4-bit equality detection without extra gates |
| Voltage Compensation | Stable switching thresholds across VEE variation - reduces calibration overhead in multi-rail systems |
| Pb-Free Compliance | RoHS-compliant PDIP-16 package (G suffix) with verified soldering profiles per SOLDERRM/D |
Applications
| Telecom Line Card Bus Arbitration | Mainframe Memory Address Comparison |
|---|---|
Use Scenario: Detecting identical address values between two 4-bit buses during memory access cycles. IC Role / Device Role / Timing Role: Quad XOR performs parallel bit-wise comparison; wire-OR output asserts match signal within 2.3 ns max enable latency. Use Value: Eliminates need for discrete comparators or FPGA logic, reducing propagation skew and board area in vintage computing systems. |
Use Scenario: Validating matching control signals across redundant processor channels in fault-tolerant mainframes. IC Role / Device Role / Timing Role: MC10H113PG acts as real-time equality monitor - outputs pulled high via 50 Ω to −2.0 V per datasheet test condition. Use Value: Achieves deterministic 1.3 ns decision latency, meeting sub-5 ns synchronization windows required by IBM System/370 derivatives. |
| Digital Test Equipment Pattern Matching | Legacy Industrial PLC I/O Handshaking |
Use Scenario: Comparing expected vs. actual 4-bit stimulus patterns in automated IC testers. IC Role / Device Role / Timing Role: Enables cycle-accurate pass/fail evaluation using XOR output summation into a single comparator input. Use Value: Supports >100 MHz pattern rates due to sub-2 ns delay budget - critical for ATE throughput at wafer probe stage. |
Use Scenario: Synchronizing status flags between isolated I/O modules in factory automation controllers. IC Role / Device Role / Timing Role: MC10H113PG validates handshake validity before enabling next state transition in ladder logic sequencers. Use Value: Delivers deterministic timing under industrial temperature swings (0–75°C), avoiding metastability in safety-critical sequencing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ECL XOR logic applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC10H113P | Same die, Pb-containing PDIP-16 package (non-RoHS) | Identical timing and logic behavior; not suitable for new RoHS-compliant designs | Select MC10H113PG when lead-free compliance is mandatory per IPC-J-STD-609. |
| SN74AS86N | TTL family, 5 V supply, 10 ns typical delay, no wire-OR outputs | Cannot perform A=B detection without external pull-up and gating; incompatible voltage levels | Only viable if system already uses TTL logic and speed requirements are relaxed to >10 ns. |
Compared with MC10H113P, MC10H113PG offers identical performance with RoHS compliance; compared with SN74AS86N, it delivers 8× faster propagation, true ECL noise immunity, and native wire-OR capability essential for hardware equality detection.
Availability
MC10H113PG is available at Aetrix Electronics and suitable for telecom infrastructure upgrades, legacy mainframe maintenance, and industrial control system refurbishment requiring stable component supply and long-term obsolescence mitigation.
Supply support for MC10H113PG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
ON Semiconductor (formerly part of Motorola's semiconductor division) is a global supplier of high-performance silicon solutions for automotive, industrial, cloud power, and sensing applications.
The MC10H113PG belongs to the legacy MECL 10H logic family, engineered for ultra-high-speed digital systems where sub-nanosecond timing precision and noise-immune differential signaling were critical - especially in 1980s–1990s telecom switches and supercomputer interconnects.
FAQ
What is the maximum operating temperature for MC10H113PG?
The MC10H113PG is rated for continuous operation from 0°C to +75°C ambient temperature, with all electrical characteristics guaranteed across this range per Table 2 and Table 3 in the official datasheet. Thermal derating begins above +75°C, and storage is supported up to +150°C for plastic packages.
Does MC10H113PG support wire-OR connection of its outputs?
Yes, MC10H113PG features open-emitter outputs (Pins 12–15) explicitly designed for wire-OR configuration. When externally pulled up to −2.0 V via 50 Ω resistors (per datasheet test condition), the summed output directly indicates 4-bit equality (A = B) without additional logic.
What is the supply voltage configuration required for MC10H113PG?
MC10H113PG requires VEE = −5.2 V ±5% on Pin 8, with VCC1 (Pin 1) and VCC2 (Pin 16) tied to 0 V (ground reference). This dual-VCC / single-VEE arrangement is standard for MECL 10H devices and enables proper biasing of internal differential pairs.
Is MC10H113PG pin-compatible with other MC10H113 variants?
Yes, MC10H113PG shares identical pinout and functionality with MC10H113P, MC10H113L, and MC10H113M - all variants use the same logic die and differ only in package type (PDIP, CDIP, SOEIAJ) and Pb content. Mechanical dimensions vary, but electrical interface is consistent.
What is the typical power dissipation of MC10H113PG under no-load conditions?
The MC10H113PG dissipates 175 mW typical under no-load conditions, as specified in the Features section of the datasheet. This value scales linearly with output loading and fan-out; actual consumption must be calculated using IE (power supply current) from Table 2 and VEE voltage.
MC10H113PG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 10H
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- XOR (Exclusive OR)
- Number of Circuits:
- 4
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- -4.94V ~ -5.46V
- Current - Quiescent (Max):
- -
- Current - Output High, Low:
- 50mA, 50mA
- Input Logic Level - Low:
- -1.48V
- Input Logic Level - High:
- -1.13V
- Max Propagation Delay @ V, Max CL:
- 1.8ns @ -5.2V, -
- Operating Temperature:
- 0°C ~ 75°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
MC10H113PG FAQ
1.How can I place an order for MC10H113PG through Aetrix?
Please submit a Request for Quotation (RFQ) for MC10H113PG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MC10H113PG reliable?
The price and inventory of MC10H113PG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC10H113PG is usually 5 days.
3.What payment methods are accepted for MC10H113PG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC10H113PG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MC10H113PG?
MC10H113PG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MC10H113PG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MC10H113PG?
For technical support, including MC10H113PG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC10H113PG requirements.
6.How does Aetrix verify that MC10H113PG is sourced from the original manufacturer or authorized distributors?
All MC10H113PG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC10H113PG meets industry standards.
7.What is the process for return or replacement of MC10H113PG?
All MC10H113PG units undergo pre-shipment inspection (PSI). If there is an issue with MC10H113PG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MC10H113PG part is unused and in its original packaging.
Return procedure for MC10H113PG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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