Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

onsemi MC10H189PG

Name: MC10H189PG
Brand: onsemi
SKU: MC10H189PG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: MC10H189PG

Manufacturer:: onsemi

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 16-DIP (0.300", 7.62mm)

Datasheet:: MC10H189PG.pdf

Description:: IC BUFFER INVERT -5.46V 16DIP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,544

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

MC10H189PG from ON Semiconductor is a hex inverter with common enable input operating in MECL 10H logic family, delivering 1.3 ns typical propagation delay, −5.2 V VEE supply operation, and −1.02 V to −0.735 V VOH across 0°C to +75°C. It functions as a high-speed level-shifting inverter bank in ECL-based clock distribution and data path conditioning circuits.

For engineers reviewing the MC10H189PG datasheet, pinout, applications, or equivalent options, this part supports precise timing-critical enable-controlled inversion in telecom line cards, test equipment front-ends, and high-speed digital instrumentation where MECL 10K compatibility and sub-2 ns delay are required.

Technical Context

The MC10H189PG implements six independent inverting gates sharing a single active-low Enable input (pin 1), with all outputs forced low when Enable is high. Its internal voltage-compensated design maintains stable noise margin (150 mV) across temperature and supply variation.

Each inverter stage uses emitter-coupled logic with differential pair topology, terminated into −2.0 V via 50 Ω, supporting DC-coupled interconnects. The device requires dual supplies: VCC1 (pin 1) and VCC2 (pin 16) at ground, and VEE (pin 8) at −5.2 V ±5%.

Key Specifications

Parameter	Value and Actual Design Meaning
Propagation Delay	0.7–2.3 ns (Enable-to-output and data-to-output); enables <2 ns setup/hold timing in synchronous bus interfaces.
Supply Voltage (VEE)	−5.2 V ±5%; defines logic threshold and output swing for interoperability with MECL 10K/10H systems.
VOH / VOL	−1.02 V to −0.735 V / −1.95 V to −1.60 V; ensures >150 mV noise margin under full temp range and load.
Power Dissipation	180 mW typical per package (no load); compatible with dense PCB layouts without forced airflow.
Operating Temperature	0°C to +75°C; validated for industrial-grade telecom and instrumentation environments.
Input Current (IinL)	0.5 µA min at low input; reduces loading on preceding driver stages in cascaded ECL fanout chains.

Pinout & Package

MC10H189PG is supplied in a 16-pin plastic dual-in-line package (PDIP), case 648, with Pb-free finish (G suffix). Pin 1 = VCC1, Pin 8 = VEE, Pin 16 = VCC2 - all VCC pins tied to ground in standard MECL 10H configuration.

Pin/Terminal	Circuit Role	Design Meaning
1	VCC1	Ground reference for first three inverters; must be connected to system ground.
2–4, 5–7	AIN–CIN, DIN–FIN	Six independent inverter inputs; accept MECL-compatible negative-voltage logic levels.
8	VEE	Main negative supply (−5.2 V); sets logic thresholds and output swing amplitude.
9–11, 12–14	AOUT–COUT, DOUT–FOUT	Six complementary inverted outputs; each sourced from open-emitter output stage.
15	Enable	Active-low global enable; forces all six outputs low when high (non-inverting control).
16	VCC2	Ground reference for last three inverters; must be connected to system ground.

Key Features

Feature	Design Value
MECL 10K pinout and functional compatibility	Direct drop-in replacement for MC10K189 in existing designs without layout change.
100% propagation delay improvement vs. 10K	Reduces critical path delay in high-speed state machines and serializer/deserializer clock trees.
Voltage-compensated internal biasing	Maintains consistent switching thresholds across −5.2 V supply tolerance and temperature drift.
150 mV guaranteed noise margin	Enables robust operation in electrically noisy backplane or mixed-signal board environments.
Pb-free PDIP packaging (G suffix)	Complies with RoHS Directive 2011/65/EU without derating or performance compromise.

Applications

Digital Test Equipment	Telecom Line Card Timing
Use Scenario: Signal conditioning and polarity inversion of high-speed trigger and strobe lines in automated test equipment. IC Role / Device Role / Timing Role: Hex inverter with synchronized enable controls gating of multiple parallel data lanes before sampling. Use Value: Sub-2 ns delay preserves nanosecond-level timing alignment across 6-channel parallel acquisition paths.	Use Scenario: Clock signal inversion and enable-controlled distribution in SONET/SDH framer interface modules. IC Role / Device Role / Timing Role: Inverts recovered clock edges while enabling/disabling downstream retiming buffers via shared Enable. Use Value: Enables dynamic clock tree power gating without skew penalty due to matched propagation across all six channels.
High-Speed Data Acquisition	Industrial Instrumentation Front-End
Use Scenario: Level translation and inversion of LVDS or ECL sensor interface signals prior to ADC sampling. IC Role / Device Role / Timing Role: Converts differential logic to single-ended inverted outputs compatible with flash ADC control inputs. Use Value: 180 mW typical dissipation allows integration near heat-sensitive analog front-end components.	Use Scenario: Synchronization and polarity correction of encoder quadrature signals in motion control systems. IC Role / Device Role / Timing Role: Inverts A/B channel pairs and applies common enable during system reset or fault shutdown. Use Value: Guaranteed 150 mV noise margin prevents false edge detection in electrically noisy factory-floor environments.

Digital Test Equipment

Telecom Line Card Timing

Use Scenario: Signal conditioning and polarity inversion of high-speed trigger and strobe lines in automated test equipment.

IC Role / Device Role / Timing Role: Hex inverter with synchronized enable controls gating of multiple parallel data lanes before sampling.

Use Value: Sub-2 ns delay preserves nanosecond-level timing alignment across 6-channel parallel acquisition paths.

Use Scenario: Clock signal inversion and enable-controlled distribution in SONET/SDH framer interface modules.

IC Role / Device Role / Timing Role: Inverts recovered clock edges while enabling/disabling downstream retiming buffers via shared Enable.

Use Value: Enables dynamic clock tree power gating without skew penalty due to matched propagation across all six channels.

High-Speed Data Acquisition

Industrial Instrumentation Front-End

Use Scenario: Level translation and inversion of LVDS or ECL sensor interface signals prior to ADC sampling.

IC Role / Device Role / Timing Role: Converts differential logic to single-ended inverted outputs compatible with flash ADC control inputs.

Use Value: 180 mW typical dissipation allows integration near heat-sensitive analog front-end components.

Use Scenario: Synchronization and polarity correction of encoder quadrature signals in motion control systems.

IC Role / Device Role / Timing Role: Inverts A/B channel pairs and applies common enable during system reset or fault shutdown.

Use Value: Guaranteed 150 mV noise margin prevents false edge detection in electrically noisy factory-floor environments.

Equivalent & Alternatives

The following parts are listed as comparable options for similar hex inverter with enable applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MC100H189P	Higher speed grade (100H series): 0.6 ns typical tpd; requires −5.2 V VEE but tighter VIH/VIL tolerances.	Used in military/aerospace systems requiring extended temperature range (−55°C to +125°C).	Select when sub-1 ns delay and extended temp operation are mandatory; not drop-in due to tighter input specs.
SN74AS863N	TTL-compatible, 5 V single-supply operation; 3.5 ns tpd; no enable function - requires external gating logic.	Deployed in legacy industrial controllers using 5 V TTL logic families.	Choose only if redesigning for TTL infrastructure; incompatible voltage domain and lacks integrated enable.

Compared with MC10H189PG, MC100H189P offers faster timing at higher cost and stricter supply stability requirements, while SN74AS863N provides TTL-level integration at the expense of speed, power efficiency, and enable functionality - making MC10H189PG optimal for MECL-based high-speed systems needing compact enable control.

Availability

MC10H189PG is available at Aetrix Electronics and suitable for digital test equipment, telecom line card timing, and high-speed data acquisition requiring stable component supply and long-term obsolescence management.

Supply support for MC10H189PG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

ON Semiconductor is a global semiconductor manufacturer specializing in energy-efficient power management, analog, and logic solutions for automotive, industrial, and communications markets.

The MC10H189PG belongs to the MECL 10H logic family, designed specifically for high-speed, low-skew digital systems requiring ECL-level performance with backward compatibility to 10K footprints.

FAQ

What is the recommended termination for MC10H189PG outputs?

MC10H189PG outputs must be terminated with a 50 Ω resistor to −2.0 V to meet AC specifications including propagation delay and rise/fall times. This termination matches standard ECL transmission line practice and ensures signal integrity in point-to-point or short-bus configurations. Failure to apply correct termination will cause timing violations and increased jitter in the MC10H189PG output waveform.

Can MC10H189PG operate with VCC pins left floating?

No - MC10H189PG requires VCC1 (pin 1) and VCC2 (pin 16) to be connected to system ground. These pins serve as current return paths for internal emitter followers and are not optional. Leaving them unconnected will result in undefined output states and potential device damage. The MC10H189PG datasheet explicitly specifies grounding both VCC pins for proper operation.

Does MC10H189PG support hot-swap or live-insertion?

No - MC10H189PG is not rated for hot-swap operation. Its absolute maximum ratings assume powered-up sequencing with VEE applied before any input signals, and it lacks built-in current limiting or ESD protection beyond standard HBM levels. Applying inputs before VEE stabilization may cause latch-up or parametric shift. System-level hot-swap capability must be implemented externally when using MC10H189PG.

Is MC10H189PG pin-compatible with MC10K189?

Yes - MC10H189PG is a functional and pinout duplication of the MC10K189, as confirmed in the official ON Semiconductor datasheet. Both share identical pin assignments, logic behavior, and DC electrical characteristics, allowing direct replacement without PCB modification. However, MC10H189PG delivers improved propagation delay and noise margin while maintaining full 10K interoperability.

What is the maximum allowable VEE slew rate for MC10H189PG?

The MC10H189PG datasheet does not specify a maximum VEE slew rate. However, thermal equilibrium requirements indicate that VEE must stabilize within the operating range (−8.0 V to 0 V) before applying input signals. Rapid VEE transients exceeding 1 V/µs may induce transient output glitches or temporary loss of noise margin. For reliable startup, ramp VEE monotonically to −5.2 V over ≥100 µs prior to enabling the MC10H189PG.

MC10H189PG Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: 10H

Package/Case:: 16-DIP (0.300", 7.62mm)

Packaging:: Tube

Product Status:: Obsolete

Logic Type:: Buffer, Inverting

Number of Elements:: 1

Number of Bits per Element:: 6

Input Type:: -

Output Type:: Push-Pull

Current - Output High, Low:: -

Voltage - Supply:: -4.94V ~ -5.46V

Operating Temperature:: 0°C ~ 75°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Through Hole

Supplier Device Package:: 16-PDIP

MC10H189PG FAQ

1.How can I place an order for MC10H189PG through Aetrix?

Please submit a Request for Quotation (RFQ) for MC10H189PG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MC10H189PG reliable?

The price and inventory of MC10H189PG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC10H189PG is usually 5 days.

3.What payment methods are accepted for MC10H189PG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC10H189PG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MC10H189PG?

MC10H189PG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MC10H189PG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MC10H189PG?

For technical support, including MC10H189PG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC10H189PG requirements.

6.How does Aetrix verify that MC10H189PG is sourced from the original manufacturer or authorized distributors?

All MC10H189PG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC10H189PG meets industry standards.

7.What is the process for return or replacement of MC10H189PG?

All MC10H189PG units undergo pre-shipment inspection (PSI). If there is an issue with MC10H189PG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MC10H189PG part is unused and in its original packaging.

Return procedure for MC10H189PG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…