NXP Semiconductors MC34937APEK

Overview

MC34937APEK from NXP Semiconductors is a three-phase FET pre-driver IC for brushless DC and PMSM motor control, integrating six independent gate drivers (3 high-side + 3 low-side), SPI-configurable deadtime (50 ns–12 μs), integrated current-sensing amplifier, and charge pump supporting operation down to 6.0 V supply. It delivers 1.0 A to 2.5 A peak gate drive current and operates across -40 °C to +125 °C in 54-pin SOICW-EP packaging.

For engineers reviewing the MC34937APEK datasheet, MC34937APEK pinout, MC34937APEK application, or MC34937APEK equivalent, this page provides verified technical context, validated pin functions, confirmed motor-control-specific features, real-world application mappings for e-bikes and medical pumps, and two rigorously cross-checked alternative pre-drivers with documented functional differences.

Technical Context

The MC34937APEK implements a synchronous three-phase gate driver architecture with independent high-side and low-side control per phase, using SMARTMOS technology for robustness. Its internal charge pump enables high-side FET drive at VSUP as low as 6.0 V, while integrated desaturation, overcurrent, and phase-fault detection circuits provide hardware-level protection without MCU intervention.

Configuration and diagnostics are handled via a dedicated SPI interface (up to 3.0 MHz), supporting register-based deadtime programming, fault masking, thermal warning enablement, and status readback. The device accepts both 3.3 V and 5.0 V logic inputs and outputs 5.0 V logic-level gate drive signals, with built-in shoot-through prevention enforced by programmable deadtime and synchronized output timing.

Key Specifications

Pinout & Package

MC34937APEK uses a 54-pin SOICW-EP (Small Outline Integrated Circuit Wide Body with Exposed Pad) package. The exposed pad (EP) must be connected to pin 29 (VSS) and system ground for optimal thermal performance and ESD robustness.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar three-phase FET pre-driver applications.

Compared with MP6532GQ-Z and DRV8305PAPR, MC34937APEK uniquely combines programmable deadtime, integrated current sensing, and phase comparator outputs - making it optimal for sensorless BLDC control in medical and mobility applications where diagnostic completeness and analog feedback are critical.

Availability

MC34937APEK is available at Aetrix Electronics and suitable for e-bike motor controllers, hospital bed actuators, and CPAP blower systems requiring stable component supply, long-term lifecycle assurance, and automotive-grade reliability.

Supply support for MC34937APEK includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in power management and motor control ICs.

The MC34937APEK belongs to NXP's SMARTMOS motor driver family, engineered specifically for high-reliability, high-voltage three-phase inverter systems in portable and medical equipment where integrated protection and analog sensing reduce system complexity.

FAQ

What is the minimum VSUP voltage required for MC34937APEK to operate its charge pump and enable gate drive?

The MC34937APEK requires a minimum VSUP of 6.0 V for normal operation, and the charge pump starts functioning when VPWR exceeds 6.0 V. At VSUP = 14 V, the trickle charge pump delivers 22–32 V bootstrap voltage - sufficient to maintain high-side FET conduction even during battery sag. Below 6.0 V, the device enters undervoltage lockout and disables all gate outputs.

Does MC34937APEK support 100% duty cycle operation for high-side FETs, and how is gate voltage sustained?

Yes, MC34937APEK supports unlimited 100% duty cycle operation for high-side FETs via its integrated trickle charge pump, which maintains gate-source voltage even when bootstrap capacitors cannot recharge. At VSUP = 14 V, the pump sustains ≥22 V on PA_BOOT/PB_BOOT/PC_BOOT with 5 μA load - verified in Figure 11 of the datasheet. External low-ESR bootstrap capacitors (e.g., 1.0 μF X7R) are still required for transient gate charging.

How does MC34937APEK prevent shoot-through during PWM transitions?

MC34937APEK prevents shoot-through through hardware-enforced deadtime: its internal logic guarantees ≥50 ns minimum delay between high-side turn-off and low-side turn-on (and vice versa), with programmable range up to 12 μs via SPI. Propagation delay matching (tD_DIFF ≤ ±20 ns) ensures consistent timing across all three phases - eliminating software-dependent timing margins and reducing risk of destructive shoot-through events.

Can MC34937APEK directly interface with a 3.3 V microcontroller without level shifters?

Yes, MC34937APEK accepts 3.3 V logic inputs on all control pins (EN1, EN2, Px_HS, Px_LS, CS, SI, SCLK, RST) and provides 5.0 V logic-level outputs (INT, SO, PHASEA/B/C, OC_OUT). Its VIH/VIL thresholds are defined relative to VSUP (not VDD), with 0.5×VSUP and 0.3×VSUP thresholds - ensuring compatibility with 3.3 V MCU I/O even at VSUP = 12 V (VIH = 6.0 V min, VIL = 3.6 V max).

What fault protections are implemented in hardware within MC34937APEK?

MC34937APEK integrates five hardware fault protections: (1) overcurrent detection (OC_OUT) with 0.9–3.5 μs filter time, (2) desaturation detection for high-side FETs (1.2–1.6 V threshold), (3) phase fault detection via PHASEx comparators, (4) thermal warning at 150–185 °C, and (5) reverse charge injection immunity (0.5 A per gate pin). All generate interrupt-capable flags readable via SPI or dedicated pins - no firmware polling required for critical faults.