NXP Semiconductors MC68020EH16E
- Part No.:
- MC68020EH16E
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 132-BQFP Bumpered
- Datasheet:
-
MC68020EH16E.pdf
- Description:
- IC MPU M680X0 166MHZ 132PQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,531
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Product details
Overview
MC68020EH16E from Motorola (later Freescale) is a 32-bit, second-generation enhanced microprocessor with on-chip 256-byte instruction cache, 32-bit data and address buses (A31–A0), and full 32-bit internal architecture. It operates at 16 MHz, supports supervisor/user privilege levels, coprocessor interface (CP0–CP3), and asynchronous bus timing for memory and I/O expansion in embedded control systems.
For engineers reviewing the MC68020EH16E datasheet, MC68020EH16E pinout, MC68020EH16E application, or MC68020EH16E equivalent, key selection considerations include clock frequency tolerance, bus arbitration support, cache enable/disable control, exception vector mapping, and compatibility with MC68881 FPU and MC68851 MMU coprocessors.
Technical Context
The MC68020EH16E implements a five-stage pipeline (fetch, decode, execute, address, writeback) with dynamic bus sizing and misaligned operand handling. It features a Harvard-style on-chip instruction cache (256 bytes, direct-mapped), no data cache, and supports both big-endian byte ordering and 32-bit linear addressing with optional MMU interfacing.
Its bus interface uses asynchronous handshake signals (AS, DS, DTACK, BR, BG, BGACK), transfer size encoding (SIZ1/SIZ0), and function code lines (FC2–FC0) to distinguish instruction fetch, data access, and space cycles. Exception processing includes 256-vector table support, stack frame formats for bus/address errors, and trace/debug primitives via emulator support signals.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Clock Frequency | 16 MHz maximum - defines instruction throughput ceiling and synchronous peripheral timing budget |
| Address Bus Width | 32-bit (A31–A0) - enables 4 GB linear address space without segmentation |
| Data Bus Width | 32-bit (D31–D0) - supports full-word transfers per cycle; dynamic sizing allows byte/word access |
| Instruction Cache | 256-byte direct-mapped - reduces average instruction fetch latency but requires software cache management |
| Privilege Model | Supervisor/User dual-mode - enforces memory protection and OS kernel isolation when used with MMU |
| Coprocessor Interface | Four CPx lines + dedicated protocol - enables concurrent execution with MC68881 FPU or MC68851 MMU |
| Bus Protocol | Asynchronous, DTACK-controlled - accommodates variable-speed memory and peripherals without clock stretching |
Pinout & Package
MC68020EH16E is housed in a 132-pin ceramic PGA (Pin Grid Array) package, designated RC suffix per Motorola ordering nomenclature. Thermal and mechanical data confirm 1.27 mm pin pitch and 39.62 mm × 39.62 mm body dimensions.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK | Primary clock input | Accepts TTL-compatible 16 MHz square wave; drives internal pipeline stages and bus timing |
| RESET | Active-low asynchronous reset | Forces processor into initial state, clears registers, and begins execution at vector 0 |
| AS | Address Strobe | Indicates valid address on A31–A0; initiates bus cycle timing sequence |
| DS | Data Strobe | Valid during read/write data transfer; synchronized with DTACK for handshaking |
| DTACK | Data Transfer Acknowledge | Peripherals assert to terminate bus cycle; enables variable-speed memory interfacing |
| BR, BG, BGACK | Bus Request/Grant control | Supports multi-master arbitration; allows DMA controllers to seize bus ownership |
| FC2–FC0 | Function Code outputs | Encode cycle type (e.g., 111 = user data space, 101 = supervisor program space) |
| CP0–CP3 | Coprocessor present lines | Signal active coprocessor status; used in conjunction with instruction decode for CP interface |
Key Features
| Feature | Design Value |
|---|---|
| Pipelined 32-bit execution unit | Enables overlapping instruction fetch/decode/execute, improving average IPC over MC68000 |
| On-chip 256-byte instruction cache | Reduces external memory bandwidth demand for sequential code; software-managed, no transparency |
| Full 32-bit address and data paths | Eliminates address/data multiplexing; simplifies PCB layout and supports burst-capable memory subsystems |
| Comprehensive exception model (256 vectors) | Supports robust OS services including virtual memory traps, privilege violations, and precise fault recovery |
| Dedicated coprocessor interface (CP0–CP3) | Allows hardware-accelerated floating-point (MC68881) or memory management (MC68851) without software polling |
| Asynchronous bus with DTACK handshake | Permits integration with slow SRAM, ROM, or custom logic without clock domain constraints |
Applications
| Industrial Motion Controller | Legacy Workstation CPU |
|---|---|
Use Scenario: Real-time servo loop execution in CNC machines using deterministic interrupt response and memory-mapped I/O. IC Role / Device Role / Timing Role: Primary CPU executing motion trajectory calculations, managing encoder feedback, and driving pulse-width modulated motor outputs. Use Value: 16 MHz clock and pipelined execution deliver sub-10 µs interrupt latency; 32-bit addressing supports large lookup tables for spline interpolation. |
Use Scenario: Host processor in early UNIX workstations (e.g., Sun-3, Apollo DN3000) requiring MMU and FPU coherency. IC Role / Device Role / Timing Role: Central compute engine interfacing with MC68851 MMU and MC68881 FPU via dedicated CP lines. Use Value: Coprocessor interface ensures atomic context save/restore during FP exceptions; supervisor/user mode enforces process isolation. |
| Communications Protocol Stack Engine | Avionics Data Acquisition Unit |
Use Scenario: Packet parsing and TCP/IP offload in router line cards with external DMA and dual-port RAM. IC Role / Device Role / Timing Role: Protocol interpreter managing buffer descriptors, checksum calculation, and interrupt-driven packet dispatch. Use Value: Asynchronous bus and BR/BG arbitration allow zero-wait-state DMA transfers while CPU processes prior frames. |
Use Scenario: Sensor fusion and health monitoring in flight-critical systems using radiation-tolerant memory and watchdog supervision. IC Role / Device Role / Timing Role: Deterministic real-time controller reading analog-to-digital converters and driving ARINC 429 transceivers. Use Value: Reset vector consistency and exception stack frame standardization enable certified fault containment per DO-254 requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit embedded microprocessor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC68020RC16 | Same die, identical 16 MHz speed grade, RC ceramic PGA package - functionally identical to MC68020EH16E | No difference; EH16E and RC16 denote same manufacturing batch and screening level per Motorola documentation | Select MC68020RC16 if sourcing legacy inventory with RC suffix marking; electrically and functionally interchangeable |
| MC68EC020RC16 | Omits A24–A31 address lines (24-bit address bus), no VPA/VMA pins, reduced power - lacks full 4 GB addressing capability | Suitable only for cost-sensitive embedded systems with ≤16 MB memory; cannot replace MC68020EH16E in workstation or MMU-based designs | Choose MC68EC020RC16 only when 24-bit addressing suffices and power/performance trade-off is acceptable |
Compared with MC68020EH16E, MC68020RC16 offers identical performance and compatibility, whereas MC68EC020RC16 sacrifices address space and coprocessor flexibility for lower cost and power - making it unsuitable as a drop-in replacement in full-featured systems.
Availability
MC68020EH16E is available at Aetrix Electronics and suitable for industrial motion control, legacy workstation repair, avionics data acquisition, and communications protocol stack development requiring stable component supply across long-lifecycle programs.
Supply support for MC68020EH16E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Motorola Semiconductor (later Freescale Semiconductor) was a pioneering U.S. semiconductor manufacturer known for the 68000 family and automotive, industrial, and communications ICs.
The MC68020EH16E belongs to the M68000 family's second-generation microprocessors, designed for high-performance embedded computing and early UNIX workstations requiring full 32-bit addressing and coprocessor extensibility.
FAQ
What is the maximum operating frequency of the MC68020EH16E?
The MC68020EH16E is rated for a maximum clock frequency of 16 MHz, as indicated by the "16" in its part number suffix. This speed grade is validated across commercial temperature range (0°C to +70°C) and defines the upper limit for reliable instruction execution, bus timing, and cache operation. Exceeding 16 MHz may cause timing violations in AS/DS/DTACK sequences or pipeline stalls.
Does the MC68020EH16E include an on-chip data cache?
No, the MC68020EH16E includes only a 256-byte on-chip instruction cache; it has no data cache. The instruction cache is direct-mapped and must be explicitly managed by software (e.g., cache invalidation after self-modifying code). Data accesses always go off-chip via the 32-bit data bus, requiring external memory design to meet timing constraints.
Which coprocessors are compatible with the MC68020EH16E?
The MC68020EH16E supports the MC68881 floating-point unit and MC68851 memory management unit via its dedicated four-line coprocessor interface (CP0–CP3) and protocol-defined primitives. These devices connect directly to the CPU bus and rely on the MC68020EH16E's exception vectoring and context save/restore instructions for seamless integration.
What package type is used for the MC68020EH16E?
The MC68020EH16E is packaged in a 132-pin ceramic Pin Grid Array (PGA) with RC suffix designation. Its mechanical dimensions are 39.62 mm × 39.62 mm, pin pitch is 1.27 mm, and it is designed for socketed insertion in high-reliability or field-upgradeable systems. The ceramic construction provides thermal stability and hermetic sealing for industrial environments.
How does the MC68020EH16E handle bus arbitration?
The MC68020EH16E implements three-signal bus arbitration using BR (Bus Request), BG (Bus Grant), and BGACK (Bus Grant Acknowledge). When another master asserts BR, the MC68020EH16E completes its current bus cycle, tri-states its address/data/control outputs, and releases the bus upon asserting BGACK - enabling DMA controllers or other processors to take ownership without system halt.
MC68020EH16E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 132-BQFP Bumpered
- Series:
- M680x0
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- 68020
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 166MHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- -
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- -
- SATA:
- -
- USB:
- -
- Voltage - I/O:
- 5.0V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 132-PQFP (46x46)
- Additional Interfaces:
- -
MC68020EH16E FAQ
1.How can I place an order for MC68020EH16E through Aetrix?
Please submit a Request for Quotation (RFQ) for MC68020EH16E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MC68020EH16E reliable?
The price and inventory of MC68020EH16E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC68020EH16E is usually 5 days.
3.What payment methods are accepted for MC68020EH16E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC68020EH16E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MC68020EH16E?
MC68020EH16E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MC68020EH16E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MC68020EH16E?
For technical support, including MC68020EH16E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC68020EH16E requirements.
6.How does Aetrix verify that MC68020EH16E is sourced from the original manufacturer or authorized distributors?
All MC68020EH16E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC68020EH16E meets industry standards.
7.What is the process for return or replacement of MC68020EH16E?
All MC68020EH16E units undergo pre-shipment inspection (PSI). If there is an issue with MC68020EH16E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MC68020EH16E part is unused and in its original packaging.
Return procedure for MC68020EH16E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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