onsemi MC74AC10N
- Part No.:
- MC74AC10N
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 14-DIP (0.300", 7.62mm)
- Datasheet:
-
MC74AC10N.pdf
- Description:
- IC GATE NAND 3CH 3-INP 14DIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,358
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MC74AC10N from onsemi is a triple 3-input NAND gate in high-performance silicon-gate CMOS technology, operating at supply voltages from 2.0 V to 6.0 V, delivering ±24 mA output drive, with propagation delays as low as 4.0 ns (tPHL/tPLH at VCC = 5.0 V, CL = 50 pF), and designed for logic-level translation and combinatorial control in industrial digital systems.
For engineers reviewing the MC74AC10N datasheet, pinout, applications, or equivalent options, this device supports fast-switching TTL- and CMOS-compatible logic design, requires no level-shifting circuitry across 3.3 V/5 V domains, and serves as a drop-in replacement for legacy 74AC10 variants in space-constrained SOIC-14 layouts.
Technical Context
The MC74AC10N implements three independent 3-input NAND gates using advanced silicon-gate CMOS process, ensuring rail-to-rail output swing and low static current (ICC ≤ 40 µA at VCC = 5.5 V). Its input thresholds scale with VCC - VIH = 2.1 V min at VCC = 3.0 V, 3.15 V min at VCC = 4.5 V - enabling robust noise immunity across voltage ranges.
Each gate exhibits matched tPLH/tPHL propagation characteristics (4.0–6.5 ns typical at 5.0 V), low input capacitance (CIN = 4.5 pF), and dynamic output capability up to ±75 mA peak (IOLD/IOHD), supporting capacitive loads and transient-driven interface buffering without external pull-ups.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Triple 3-input NAND gate - enables compact implementation of AND-NOT logic trees and enable/disable control blocks |
| Supply Voltage Range | 2.0 V to 6.0 V - supports direct interfacing with 3.3 V and 5 V logic families without level shifters |
| Output Drive | ±24 mA - sufficient to directly drive LEDs, small MOSFET gates, or multiple 74AC inputs (fan-out ≥ 10) |
| Propagation Delay | 4.0 ns typical (tPHL/tPLH, VCC = 5.0 V, CL = 50 pF) - enables sub-100 MHz combinational timing in synchronous designs |
| Input Thresholds | VIH = 2.1 V min @ 3.0 V, 3.15 V min @ 4.5 V - ensures reliable switching across mixed-voltage system interfaces |
| Quiescent Current | ICC ≤ 40 µA @ VCC = 5.5 V - maintains ultra-low standby power in battery-backed or always-on logic subsystems |
| ESD Rating | HBM > 2000 V - provides robust handling margin during PCB assembly and field service operations |
Pinout & Package
MC74AC10N is supplied in a 14-lead SOIC package (Case 751A), with standard dual-inline pin spacing (1.27 mm pitch), 8.75 mm body width, and 3.9 mm height - compatible with automated pick-and-place and reflow soldering per IPC-J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | Input A, B, C of Gate 1 | Three logic inputs for first NAND gate; all CMOS-compatible with high-impedance, low-leakage operation |
| 4 | Output Y1 | Inverted AND of pins 1–3; drives loads up to 24 mA sink/source with rail-aligned VOH/VOL |
| 5, 6, 13 | Input A, B, C of Gate 2 | Independent 3-input set; electrically isolated from Gate 1; identical AC/DC specs |
| 12 | Output Y2 | Second NAND output; shares same VCC/GND rails but no internal coupling to other gates |
| 8, 9, 10 | Input A, B, C of Gate 3 | Third independent 3-input NAND; pinout optimized for minimal trace crossovers in dense routing |
| 11 | Output Y3 | Third output; supports concurrent multi-channel logic decisions without timing skew between gates |
| 7 | GND | Ground reference for all logic thresholds and output stages; must be low-impedance for noise immunity |
| 14 | VCC | Positive supply rail; decoupling capacitor (0.1 µF ceramic) required within 5 mm for stable AC performance |
Key Features
| Feature | Design Value |
|---|---|
| Pb-free SOIC-14 packaging | Complies with RoHS Directive 2011/65/EU and JEDEC J-STD-020 moisture sensitivity Level 1 - suitable for lead-free reflow without preconditioning |
| Wide VCC range (2.0–6.0 V) | Eliminates need for separate voltage regulators when interfacing 3.3 V microcontrollers with 5 V peripherals |
| High-speed propagation (4.0 ns typ) | Enables real-time decoding of 100+ MHz clocked address/data buses in FPGA glue logic or bus arbitration circuits |
| ±24 mA output drive | Directly controls small-signal MOSFETs (e.g., 2N7002) or drives 10+ 74AC inputs without fanout buffers |
| Low input leakage (±1.0 µA max) | Preserves signal integrity in high-impedance sensor interface nodes or battery-powered wake-up logic |
| CMOS input compatibility | Accepts clean TTL outputs while rejecting noise below 0.9 V (VIL max @ 3.0 V), reducing false triggering |
Applications
| Industrial PLC I/O Expansion | Microcontroller Peripheral Enable Logic |
|---|---|
Use Scenario: Adding discrete digital output channels to a programmable logic controller via optocoupler-isolated driver banks. IC Role / Device Role / Timing Role: NAND gate used as active-low enable decoder - three MCU GPIO lines select one of eight output drivers via 3-bit binary encoding. Use Value: Reduces firmware overhead by offloading address decoding to hardware; propagation delay <6.5 ns ensures deterministic response under 10 kHz scan cycles. |
Use Scenario: Controlling power sequencing and reset assertion for multiple peripheral ICs (ADC, DAC, transceiver) on an embedded board. IC Role / Device Role / Timing Role: Triple NAND implements synchronized enable gating - two MCU control bits plus global enable generate three independent peripheral power-on signals. Use Value: Eliminates software-based delay loops; rail-to-rail VOH/VOL guarantees full logic swing into 10 kΩ enable inputs across temperature (−40°C to +85°C). |
| Digital Audio Clock Domain Isolation | Legacy Bus Address Decoding |
Use Scenario: Preventing clock domain crossing glitches between a 48 MHz audio codec clock and a 24 MHz DSP core clock. IC Role / Device Role / Timing Role: NAND gate configured as edge-triggered synchronizer - input sampled on rising edge of slow clock, output asserted only after two consecutive high samples. Use Value: Input hysteresis and low propagation skew (<0.5 ns mismatch between gates) suppress metastability without external flip-flops. |
Use Scenario: Translating 16-bit address bus signals into chip-select lines for memory-mapped peripherals in retro-computing or test equipment. IC Role / Device Role / Timing Role: Three independent NANDs decode upper address bits (A13–A15) to generate CS0–CS2 for SRAM, EPROM, and I/O port chips. Use Value: Guaranteed setup/hold timing margins at 5 V allow reliable operation up to 8 MHz bus speeds without added wait states. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple 3-input NAND gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74AC10N | Same logic function, pinout, and AC/DC specs; TI-manufactured with identical SOIC-14 footprint and 2.0–6.0 V operation | No functional deviation - validated for drop-in use in existing MC74AC10N layouts | Select when sourcing from TI-authorized channels or requiring TI-specific qualification documentation |
| 74VHC10N | Higher speed (tPD = 3.5 ns typ @ 5 V), lower ICC (2 µA max), but VIH/VIL thresholds fixed at 3.5 V/1.5 V - not VCC-scaled | Requires stable 5 V supply; unsuitable for 3.3 V-only systems without level translation | Prefer for high-frequency timing-critical paths where supply is strictly 5 V and leakage must be minimized |
Compared with SN74AC10N, MC74AC10N offers identical electrical behavior and layout compatibility, while 74VHC10N trades supply flexibility for marginal speed gain and lower quiescent current - making MC74AC10N optimal for mixed-voltage industrial control where reliability and voltage adaptability outweigh nanosecond-level timing gains.
Availability
MC74AC10N is available at Aetrix Electronics and suitable for industrial automation, embedded control, and test instrumentation requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.
Supply support for MC74AC10N includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, logic, and sensing solutions for automotive, industrial, and cloud infrastructure markets.
The MC74AC10N belongs to the 74AC logic family - engineered for high-speed, low-power CMOS operation in industrial environments where wide supply tolerance and robust ESD protection are essential.
FAQ
What is the maximum operating frequency supported by the MC74AC10N?
The MC74AC10N does not specify a maximum clock frequency because it is a combinational logic device without internal clocking. Its usable toggle rate depends on propagation delay and load capacitance: with CL = 50 pF and VCC = 5.0 V, tPHL/tPLH is 4.0–6.5 ns, enabling reliable operation in logic paths up to approximately 100 MHz for simple gate chains. For precise timing analysis, designers must calculate worst-case path delay including trace capacitance and fanout.
Can the MC74AC10N operate at 3.3 V and interface directly with 5 V TTL devices?
Yes, the MC74AC10N operates over 2.0–6.0 V and features CMOS inputs with VIL = 0.9 V max and VIH = 2.1 V min at VCC = 3.0 V - well within TTL output voltage ranges (0.4 V low, 2.4 V high). Its outputs swing rail-to-rail, producing VOH ≈ 3.3 V and VOL ≈ 0 V at 3.3 V supply, which are recognized as valid HIGH/LOW by 5 V TTL inputs. No level-shifter is needed for bidirectional interfacing.
Is the MC74AC10N pin-compatible with the MC74ACT10?
No, the MC74AC10N and MC74ACT10 are not pin-compatible. While both are triple 3-input NANDs in SOIC-14 packages, the MC74ACT10 has TTL-compatible inputs (VIH = 2.0 V fixed, not VCC-scaled), resulting in different DC input thresholds and slightly modified AC behavior. They share identical pinouts and package dimensions, but substituting one for the other may cause logic errors if input voltage levels fall outside the respective VIH/VIL windows.
What is the thermal resistance (θJA) of the MC74AC10N in SOIC-14 package?
The MC74AC10N in SOIC-14 package (Case 751A) has a junction-to-ambient thermal resistance (θJA) of 116°C/W, as specified in the Maximum Ratings table. This value assumes standard JEDEC test conditions (single-layer board, 1 in² copper pad). Actual θJA in end-user PCBs will vary based on copper area, airflow, and adjacent heat sources - derating is recommended above 70°C ambient for continuous 50 mW dissipation.
Does the MC74AC10N require external pull-up or pull-down resistors on unused inputs?
Yes, all unused inputs of the MC74AC10N must be terminated to a defined logic level - either VCC or GND - using external resistors (typically 1–10 kΩ). Floating CMOS inputs can drift into the linear region, causing excessive supply current, oscillation, or increased EMI susceptibility. Leaving inputs unconnected violates the Absolute Maximum Ratings for input voltage and risks latch-up or premature device failure.
MC74AC10N Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74AC
- Package/Case:
- 14-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- NAND Gate
- Number of Circuits:
- 3
- Number of Inputs:
- 3
- Features:
- -
- Voltage - Supply:
- 2V ~ 6V
- Current - Quiescent (Max):
- 4 µA
- Current - Output High, Low:
- 24mA, 24mA
- Input Logic Level - Low:
- 0.9V ~ 1.65V
- Input Logic Level - High:
- 2.1V ~ 3.85V
- Max Propagation Delay @ V, Max CL:
- 7ns @ 5V, 50pF
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 14-PDIP
MC74AC10N FAQ
1.How can I place an order for MC74AC10N through Aetrix?
Please submit a Request for Quotation (RFQ) for MC74AC10N on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MC74AC10N reliable?
The price and inventory of MC74AC10N are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC74AC10N is usually 5 days.
3.What payment methods are accepted for MC74AC10N?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC74AC10N transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MC74AC10N?
MC74AC10N orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MC74AC10N order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MC74AC10N?
For technical support, including MC74AC10N datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC74AC10N requirements.
6.How does Aetrix verify that MC74AC10N is sourced from the original manufacturer or authorized distributors?
All MC74AC10N products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC74AC10N meets industry standards.
7.What is the process for return or replacement of MC74AC10N?
All MC74AC10N units undergo pre-shipment inspection (PSI). If there is an issue with MC74AC10N, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MC74AC10N part is unused and in its original packaging.
Return procedure for MC74AC10N:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MC74AC10N Tags
-
SN74LVC1G14DBVR
Texas Instruments
-
SN74LVC1G14DCKR
Texas Instruments
-
SN74AHC1G14DBVR
Texas Instruments
-
SN74LVC1G08DBVR
Texas Instruments
-
SN74LVC1G08DCKR
Texas Instruments
-
SN74LVC1G32DCKR
Texas Instruments
-
SN74LVC1G04DBVR
Texas Instruments
.jpg)
-
74LVC1G08GW,125
Nexperia USA Inc.
-
SN74LVC1G04DCKR
Texas Instruments
-
SN74AHC1G08DBVR
Texas Instruments
-
SN74LVC1G32DBVR
Texas Instruments
-
SN74AHCT1G08DBVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

