onsemi MC74AC125N
- Part No.:
- MC74AC125N
- Manufacturer:
- onsemi
- Package:
- 14-DIP (0.300", 7.62mm)
- Datasheet:
-
MC74AC125N.pdf
- Description:
- IC BUFF NON-INVERT 6V 14DIP
- Quantity:
- Payment:

- Shipping:

Inventory:4,601
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Product details
Overview
MC74AC125N from onsemi is a quad 3-state buffer with low-enable control, designed for bidirectional data bus isolation and signal routing in CMOS logic systems. It operates from 2.0 V to 6.0 V, delivers ±24 mA output drive, features 7.5 ns max propagation delay at 5.0 V, and supports industrial temperature range (−40°C to +85°C). It is used in microcontroller peripheral interfacing and memory address/data bus buffering.
For engineers reviewing the MC74AC125N datasheet, pinout, applications, or equivalent options, key selection considerations include supply voltage compatibility (2.0–6.0 V), 3-state enable polarity (active-low), output drive strength (±24 mA), and SOIC-14 package thermal performance (θJA = 116°C/W).
Technical Context
The MC74AC125N implements four independent non-inverting buffers, each with separate active-low 3-state enable (Bn input controls On output state). Its silicon-gate CMOS process ensures low static power consumption (ICC ≤ 80 µA) and high noise immunity (VIH = 2.1 V min at VCC = 3.0 V).
Each channel functions as a controlled pass-through: when Bn = LOW, On follows An; when Bn = HIGH, On enters high-impedance state. Input thresholds are CMOS-compatible (not TTL), distinguishing it from the MC74ACT125 variant.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 6.0 V - supports mixed-voltage system interfacing (e.g., 3.3 V logic driving 5 V bus) |
| Output Drive Strength | ±24 mA - sufficient to drive standard CMOS loads and short PCB traces without external buffering |
| Propagation Delay | 7.5 ns max (VCC = 5.0 V, CL = 50 pF) - enables reliable operation up to ~50 MHz data rates in buffered paths |
| Input Thresholds | VIH = 2.1 V min @ 3.0 V VCC - ensures robust high-level recognition across voltage corners |
| Quiescent Current | 80 µA max - enables low-power standby in battery-backed or energy-sensitive applications |
| Operating Temperature | −40°C to +85°C - qualified for industrial-grade embedded control and instrumentation environments |
| ESD Rating | >2000 V HBM - provides baseline handling robustness during assembly and field service |
Pinout & Package
MC74AC125N is supplied in a 14-lead SOIC package (Case 751A), with 1.27 mm pitch, 8.75 mm × 3.90 mm body, and 1.75 mm max height. Pin 1 is top-left corner (notch/indentation side), with pins numbered counter-clockwise.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | A0, A1, A2, A3 | Data inputs - routed directly to corresponding outputs when enable is active |
| 2, 5, 11, 14 | B0, B1, B2, B3 | Active-low 3-state enables - LOW enables output; HIGH forces high-Z |
| 3, 6, 12, 9 | O0, O1, O2, O3 | Buffered outputs - non-inverting, 3-state, capable of sourcing/sinking 24 mA |
| 7 | GND | Ground reference - must be low-impedance connection for noise immunity and timing stability |
| 14 | VCC | Positive supply - decoupling capacitor (0.1 µF ceramic) required within 5 mm of this pin |
Key Features
| Feature | Design Value |
|---|---|
| Quad independent 3-state buffers | Enables simultaneous control of four isolated data paths without inter-channel crosstalk |
| CMOS-compatible input thresholds | Eliminates need for level-shifting when interfacing with other AC-series or modern low-voltage logic |
| Pb-free SOIC-14 packaging | Meets RoHS Directive 2011/65/EU and JEDEC J-STD-020 moisture sensitivity Level 1 |
| High noise margin (typ. 45%) | Ensures reliable switching under EMI-prone conditions such as motor drives or switching power supplies |
| Low dynamic power dissipation | CPD = 45 pF - minimizes switching current draw in high-frequency bus applications |
Applications
| Microcontroller Bus Isolation | Memory Address Latching |
|---|---|
|
Use Scenario: Isolating GPIO expansion ports between an MCU and external peripherals to prevent contention during reset or sleep modes. IC Role / Device Role / Timing Role: Quad buffer acts as direction-controlled gate for 4-bit parallel data lines, with per-channel enable allowing selective activation. Use Value: Prevents back-driving of MCU pins during hot-swap events and reduces I/O leakage current by 95% versus direct connection. |
Use Scenario: Driving address lines to multiple SRAM chips sharing a common data bus in a compact embedded controller. IC Role / Device Role / Timing Role: Buffers isolate address decoder outputs from capacitive loading of long traces and multiple chip selects. Use Value: Maintains address setup/hold timing integrity with <7.5 ns delay variation across all four channels. |
| Industrial Sensor Interface | Digital Signal Multiplexing |
|
Use Scenario: Aggregating digital outputs from four discrete sensors (e.g., limit switches, proximity detectors) into a single monitored bus. IC Role / Device Role / Timing Role: Each buffer channel conditions and isolates one sensor signal before multiplexing onto shared diagnostic line. Use Value: Enables individual sensor disablement for maintenance without disrupting remaining channels' operation. |
Use Scenario: Selectively routing test signals from one of four internal sources to a common debug port in FPGA-based test equipment. IC Role / Device Role / Timing Role: Acts as a 4:1 multiplexer via enable control, with non-inverting path preserving signal polarity. Use Value: Eliminates need for discrete logic gates or CPLD resources while maintaining sub-10 ns signal path skew. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC74AC125DR2G | Same die, tape-and-reel packaging (2500 pcs), identical electrical specs and SOIC-14 footprint | No functional difference; optimized for automated SMT production vs. manual prototyping | Select MC74AC125DR2G for volume manufacturing; MC74AC125N is rail-packaged (55 pcs) for evaluation and low-volume builds |
| SN74AC125N | Texas Instruments variant with identical pinout, AC specs, and 2.0–6.0 V operation; VOH spec tighter (2.9 V min @ 3.0 V) | Drop-in replacement in TI-centric designs; same thermal resistance but different marking and traceability | Choose SN74AC125N only if TI's qualification documentation or supply chain integration is required |
Compared with MC74AC125N, MC74AC125DR2G offers identical performance in scalable packaging, while SN74AC125N provides a second-source option with marginally improved high-level output voltage - both require no PCB changes but differ in logistics and compliance reporting.
Availability
MC74AC125N is available at Aetrix Electronics and suitable for industrial control interfaces, microcontroller peripheral expansion, and memory subsystem buffering requiring stable component supply across extended temperature ranges and multi-year production cycles.
Supply support for MC74AC125N includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, logic, and sensing solutions for automotive, industrial, and cloud infrastructure markets.
The MC74AC125N belongs to the 74AC logic family, engineered for high-speed, low-power CMOS operation in space-constrained industrial and instrumentation systems where reliability across temperature extremes is critical.
FAQ
What is the maximum operating supply voltage for MC74AC125N?
The MC74AC125N supports a DC supply voltage range of 0.5 V to +6.5 V, with recommended operation between 2.0 V and 6.0 V. Absolute maximum VCC is +6.5 V; exceeding this risks permanent damage. For sustained reliability, operation above 6.0 V is not advised even if within absolute maximum ratings.
Does MC74AC125N support TTL-level inputs?
No, MC74AC125N does not support TTL-level inputs. Its input thresholds are CMOS-compatible (e.g., VIH = 2.1 V min at VCC = 3.0 V). For TTL compatibility, use the pin-compatible MC74ACT125 variant, which specifies VIH = 2.0 V min at VCC = 4.5 V.
What is the function of pin 2, pin 5, pin 11, and pin 14 on MC74AC125N?
On MC74AC125N, pins 2, 5, 11, and 14 are the active-low 3-state enable inputs (B0, B1, B2, B3). When pulled LOW, they enable the corresponding buffer output (O0–O3) to follow its A-input; when HIGH, the output enters high-impedance state. These pins are not tied together internally and must be controlled independently.
Can MC74AC125N drive a 50 pF load at 5.0 V with guaranteed timing?
Yes, MC74AC125N is characterized for CL = 50 pF at VCC = 5.0 V, with tPLH/tPHL ≤ 7.0 ns (max) and tPZH/tPZL ≤ 8.0 ns (max) over −40°C to +85°C. This makes it suitable for driving standard PCB traces and multiple CMOS inputs without timing degradation.
Is MC74AC125N RoHS compliant and lead-free?
Yes, MC74AC125N is Pb-free and RoHS-compliant, indicated by the "G" suffix in ordering codes (e.g., MC74AC125DG). It meets JEDEC J-STD-020 moisture sensitivity Level 1 and is qualified for reflow soldering per IPC/JEDEC J-STD-020.
MC74AC125N Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74AC
- Package/Case:
- 14-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 24mA, 24mA
- Voltage - Supply:
- 2V ~ 6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 14-PDIP
MC74AC125N FAQ
1.How can I place an order for MC74AC125N through Aetrix?
Please submit a Request for Quotation (RFQ) for MC74AC125N on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MC74AC125N reliable?
The price and inventory of MC74AC125N are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC74AC125N is usually 5 days.
3.What payment methods are accepted for MC74AC125N?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC74AC125N transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MC74AC125N?
MC74AC125N orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MC74AC125N order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MC74AC125N?
For technical support, including MC74AC125N datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC74AC125N requirements.
6.How does Aetrix verify that MC74AC125N is sourced from the original manufacturer or authorized distributors?
All MC74AC125N products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC74AC125N meets industry standards.
7.What is the process for return or replacement of MC74AC125N?
All MC74AC125N units undergo pre-shipment inspection (PSI). If there is an issue with MC74AC125N, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MC74AC125N part is unused and in its original packaging.
Return procedure for MC74AC125N:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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