onsemi MC74AC652DWR2
- Part No.:
- MC74AC652DWR2
- Manufacturer:
- onsemi
- Package:
- 24-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
MC74AC652DWR2.pdf
- Description:
- IC TXRX NON-INVERT 6V 24SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:330
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MC74AC652DWR2 from onsemi is an octal registered bus transceiver with non-inverting 3-state outputs, implementing dual-directional data flow between A and B buses via independent D-type flip-flop registers. It supports real-time or stored-data transfer, operates at 2.0–6.0 V supply, delivers ±24 mA output drive, and is housed in a Pb-free SOIC-24 package. It is used in bidirectional data buffering and register-controlled bus isolation in industrial control backplanes.
For engineers reviewing the MC74AC652DWR2 datasheet, pinout, applications, or equivalent options, key selection criteria include clocked register storage capability, simultaneous A/B bus multiplexing, 3-state output control timing, and compatibility with 5 V TTL/CMOS logic systems.
Technical Context
The MC74AC652DWR2 integrates two independent 8-bit register banks (A and B), each with dedicated clock (CAB/CBA), select (SAB/SBA), and output-enable (GAB/GBA) controls. Its logic enables four distinct data-handling modes: real-time A→B or B→A transfer, store-from-A-and-B, or store-to-both-registers - all synchronized to LOW-to-HIGH clock transitions.
It features true non-inverting data paths, full 3-state output control per bus direction, and DC electrical characteristics compliant with AC logic families: VIH = 2.1 V (min) at VCC = 3.0 V, VOL = 0.44 V (max) at IOL = 24 mA, and propagation delays as low as 1.5 ns (tPHL, VCC = 5.0 V, CL = 50 pF).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | Octal registered transceiver with dual independent storage registers and 3-state outputs |
| Supply Voltage Range | 2.0 V to 6.0 V - supports mixed-voltage system interfacing and legacy 5 V designs |
| Output Drive | ±24 mA - sufficient to directly drive standard TTL loads without external buffers |
| Propagation Delay | 1.5 ns (min tPHL, VCC = 5.0 V) - enables high-speed synchronous bus handshaking |
| Input Thresholds | VIH = 2.1 V (min at VCC = 3.0 V); VIL = 0.9 V (max) - ensures noise margin in noisy industrial environments |
| Package | SOIC-24 (Case 751E), 300 mil width - industry-standard footprint compatible with automated PCB assembly |
| ESD Rating | HBM > 2000 V - provides robust handling during manufacturing and board-level integration |
Pinout & Package
MC74AC652DWR2 is packaged in a Pb-free 24-pin SOIC (Small Outline Integrated Circuit), case 751E, 300 mil body width, with standard JEDEC-compliant dimensions (D = 15.25–15.54 mm, E1 = 7.40–7.60 mm, e = 1.27 mm pitch).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A7 | A-bus data inputs/outputs | Bi-directional I/O pins for A-side register interface; driven by internal register or passed through in real-time mode |
| B0–B7 | B-bus data inputs/outputs | Bi-directional I/O pins for B-side register interface; functionally symmetric to A0–A7 |
| CAB, CBA | Register clock inputs | LOW-to-HIGH edge-triggered clocks that load data from A or B bus into respective registers |
| SAB, SBA | Data path select inputs | Control whether output reflects real-time bus data (S = H) or stored register data (S = L) |
| GAB, GBA | Output enable inputs | Active-low enables 3-state output drivers for A→B (GAB) and B→A (GBA) directions |
| VCC, GND | Power supply terminals | Single 2.0–6.0 V supply; no separate ground for logic vs. output sections |
Key Features
| Feature | Design Value |
|---|---|
| Independent A/B registers | Enables asynchronous data capture on either bus without affecting the other - critical for handshake-free interprocessor communication |
| Multiplexed real-time/stored transfer | Per-pin select (SAB/SBA) allows dynamic switching between live bus monitoring and buffered register readout within same cycle |
| Non-inverting data path | Preserves signal polarity across both directions - eliminates need for external inversion logic in protocol-conforming interfaces |
| 3-state output control | Dual independent enables (GAB/GBA) permit directional bus arbitration without external logic or contention risk |
| Pb-free SOIC-24 package | Meets RoHS Directive 2011/65/EU and supports lead-free reflow profiles up to 260 °C (10 s) |
Applications
| Industrial Backplane Interface | Microcontroller Bus Expansion |
|---|---|
|
Use Scenario: Isolating and extending parallel address/data buses between PLC CPU modules and I/O carrier boards. IC Role / Device Role / Timing Role: Registered transceiver providing clock-synchronized data latching and direction-controlled 3-state bus driving. Use Value: Eliminates bus contention during hot-swap events and enables deterministic timing for multi-cycle memory-mapped peripheral access. |
Use Scenario: Adding external SRAM or peripheral ICs to an MCU with limited GPIO or bus pins. IC Role / Device Role / Timing Role: Bidirectional bus buffer with register hold capability to decouple MCU timing from slower peripherals. Use Value: Allows MCU to initiate burst transfers while holding data stable for peripherals with longer setup/hold requirements. |
| Legacy System Data Bridge | Test Equipment Signal Routing |
|
Use Scenario: Interfacing 5 V TTL-based instrumentation subsystems with modern 3.3 V FPGA controllers. IC Role / Device Role / Timing Role: Level-tolerant transceiver with register staging to absorb voltage-domain skew and clock domain mismatches. Use Value: Provides clean, glitch-free data handoff without requiring external level shifters or synchronizers. |
Use Scenario: Configurable signal routing matrix in automated test equipment (ATE) for stimulus/response path selection. IC Role / Device Role / Timing Role: Programmable 8-bit data switch with storage, enabling pre-loaded test vectors to be applied on demand. Use Value: Reduces test pattern generation latency by storing vectors locally and releasing them synchronously to DUT pins. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar octal registered transceiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC74ACT652DWR2G | TTL-compatible inputs (VIH = 2.0 V min at VCC = 4.5 V); otherwise identical pinout, timing, and register architecture | Better suited for mixed-logic systems with legacy TTL drivers; higher input threshold improves noise immunity in noisy digital environments | Select when interfacing with 5 V TTL sources or where guaranteed VIH margin > 2.0 V is required |
| SN74ABT652N | Higher drive (±64 mA), ABT logic family, different AC timing (tPLH/tPHL ~1.8 ns min), same SOIC-24 pinout but not functionally identical register control | Designed for high-speed backplane loading; lacks simultaneous dual-register store capability of MC74AC652DWR2 | Choose only if higher output current is mandatory and register independence is not required |
Compared with MC74ACT652DWR2G and SN74ABT652N, the MC74AC652DWR2 offers optimal balance of CMOS input compatibility, deterministic register behavior, and industrial-grade timing margins - making it preferred for deterministic bus isolation where input voltage flexibility and dual-register autonomy are essential.
Availability
MC74AC652DWR2 is available at Aetrix Electronics and suitable for industrial automation backplanes, microcontroller bus expansion, legacy system bridging, and ATE signal routing requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for MC74AC652DWR2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The MC74AC652DWR2 belongs to onsemi's legacy AC logic family, designed specifically for high-reliability, register-controlled bidirectional data transfer in industrial control and instrumentation systems requiring deterministic timing and robust noise immunity.
FAQ
What is the maximum clock frequency supported by the MC74AC652DWR2?
The MC74AC652DWR2 does not specify a maximum clock frequency in its datasheet; instead, it defines minimum pulse width (tw = 6.0 ns min at VCC = 5.0 V) and setup/hold times (ts = 8.0 ns, th = 2.5 ns). These parameters support reliable operation up to approximately 83 MHz in ideal conditions, though actual system-level timing must account for board trace delays and load capacitance. The MC74AC652DWR2 is optimized for synchronous bus control rather than continuous high-frequency clocking.
Does the MC74AC652DWR2 support 3.3 V operation?
Yes, the MC74AC652DWR2 supports 3.3 V operation within its specified supply range of 2.0 V to 6.0 V. At VCC = 3.3 V, VIH is guaranteed ≥ 2.1 V and VOL ≤ 0.44 V at IOL = 24 mA, ensuring interoperability with standard 3.3 V CMOS logic. Input thresholds remain valid, and propagation delays increase modestly versus 5 V operation - confirmed in the AC Characteristics table for VCC = 3.0 V.
How does the MC74AC652DWR2 differ from the MC74AC652DWG variant?
The MC74AC652DWR2 and MC74AC652DWG share identical electrical specifications, pinout, and functionality. The difference lies solely in packaging and shipping format: MC74AC652DWR2 is supplied in 1000-unit tape-and-reel packaging (R2 suffix), while MC74AC652DWG is shipped in 30-unit rail packaging (G suffix). Both are Pb-free SOIC-24 devices with case number 751E and identical marking conventions.
Can the MC74AC652DWR2 operate with mixed voltage supplies on A and B buses?
No - the MC74AC652DWR2 has a single VCC pin and is not designed for mixed-supply operation. Both A and B buses must operate at the same logic voltage level referenced to the common VCC and GND. While the device tolerates input voltages from −0.5 V to VCC + 0.5 V, sustained operation outside VCC violates absolute maximum ratings and risks latch-up or reliability degradation. For true level translation, a dedicated bus transceiver like the TXB0304 is required.
Is the MC74AC652DWR2 pin-compatible with the 74LS652 or 74F652?
No - the MC74AC652DWR2 is not pin-compatible with the 74LS652 or 74F652. Although all three are octal transceivers, they differ in pin assignment: the LS/F versions use different clock, select, and enable pin mappings (e.g., 74LS652 uses CLK, S, and OE pins in distinct locations). The MC74AC652DWR2 follows the AC/ACT652-specific pinout shown in Figure 5, with CAB/CBA, SAB/SBA, and GAB/GBA assigned to specific SOIC-24 positions - substitution requires PCB redesign.
MC74AC652DWR2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74AC
- Package/Case:
- 24-SOIC (0.295", 7.50mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Transceiver, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 8
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 24mA, 24mA
- Voltage - Supply:
- 2V ~ 6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-SOIC
MC74AC652DWR2 FAQ
1.How can I place an order for MC74AC652DWR2 through Aetrix?
Please submit a Request for Quotation (RFQ) for MC74AC652DWR2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MC74AC652DWR2 reliable?
The price and inventory of MC74AC652DWR2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC74AC652DWR2 is usually 5 days.
3.What payment methods are accepted for MC74AC652DWR2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC74AC652DWR2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MC74AC652DWR2?
MC74AC652DWR2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MC74AC652DWR2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MC74AC652DWR2?
For technical support, including MC74AC652DWR2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC74AC652DWR2 requirements.
6.How does Aetrix verify that MC74AC652DWR2 is sourced from the original manufacturer or authorized distributors?
All MC74AC652DWR2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC74AC652DWR2 meets industry standards.
7.What is the process for return or replacement of MC74AC652DWR2?
All MC74AC652DWR2 units undergo pre-shipment inspection (PSI). If there is an issue with MC74AC652DWR2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MC74AC652DWR2 part is unused and in its original packaging.
Return procedure for MC74AC652DWR2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MC74AC652DWR2 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

