Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

onsemi MC74ACT652N

Name: MC74ACT652N
Brand: onsemi
SKU: MC74ACT652N
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: MC74ACT652N

Manufacturer:: onsemi

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 24-DIP (0.300", 7.62mm)

Datasheet:: MC74ACT652N.pdf

Description:: IC TXRX NON-INVERT 5.5V 24DIP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,045

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

MC74ACT652N from onsemi is an octal registered transceiver with 3-state non-inverting outputs, designed for bidirectional data bus interfacing between A and B buses in TTL-compatible systems. It provides real-time or registered data transfer, independent A/B register storage, and supports ±24 mA output drive at 5 V. Used in industrial control backplanes and legacy microprocessor bus expansion.

For engineers reviewing the MC74ACT652N datasheet, pinout, applications, or equivalent options, key selection considerations include clock-controlled register loading (CAB/CBA), dual-directional 3-state enable (GAB/GBA), TTL-compatible input thresholds, propagation delay ≤16.5 ns at 5 V, and SOIC-24 package compatibility with legacy DIP-24 footprints.

Technical Context

The MC74ACT652N integrates two independent 8-bit D-type flip-flop registers-one per bus-enabling simultaneous or selective storage of A- or B-bus data on LOW-to-HIGH clock transitions (CAB or CBA). Its logic supports four distinct data-handling modes: real-time A→B, real-time B→A, stored-A→B, and stored-B→A transfers.

Control is implemented via three dedicated signal pairs: SAB/SBA selects data path direction (real-time vs. registered), GAB/GBA enables/disables A→B or B→A outputs independently, and CAB/CBA clocks load data into respective registers. All outputs are 3-state, with TTL-compatible inputs (VIH = 2.0 V min, VIL = 0.8 V max at VCC = 5 V).

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage	4.5 V to 5.5 V - ensures compatibility with standard TTL and 5 V CMOS logic rails without level shifting.
Output Drive	±24 mA - supports direct connection to multiple TTL loads or moderate-capacitance buses without external buffers.
Propagation Delay	≤16.5 ns (max, TA = −40°C to +85°C, CL = 50 pF) - enables reliable operation in 25 MHz+ synchronous bus environments.
Input Compatibility	TTL-level - accepts standard 0.8 V / 2.0 V logic thresholds, eliminating need for input conditioning in mixed-logic systems.
3-State Enable	Independent GAB & GBA controls - allows asymmetric bus arbitration where A→B and B→A paths are enabled/disabled separately.
Operating Temperature	−40°C to +85°C - qualified for industrial ambient conditions without derating.
Package	SOIC-24 (Case 751E) - surface-mount footprint with 15.5 mm × 7.5 mm body, compatible with automated assembly and legacy DIP-24 layouts via adapter.

Pinout & Package

MC74ACT652N is housed in a 24-lead SOIC (Small Outline Integrated Circuit) package, case 751E, with 1.27 mm pitch, Pb-free finish, and moisture sensitivity level 1. Pin 1 is marked by a notch or dot; top view orientation follows standard SOIC convention.

Pin/Terminal	Circuit Role	Design Meaning
A0–A7	A-bus data inputs/outputs	Bidirectional I/O pins for A-side bus; function as inputs when storing to register A, outputs when driving A bus from register A.
B0–B7	B-bus data inputs/outputs	Bidirectional I/O pins for B-side bus; function as inputs when storing to register B, outputs when driving B bus from register B.
CAB	Register A clock input	LOW-to-HIGH transition loads data from A0–A7 into register A; edge-triggered, asynchronous to CBA.
CBA	Register B clock input	LOW-to-HIGH transition loads data from B0–B7 into register B; edge-triggered, asynchronous to CAB.
SAB	A→B data path select	LOW enables real-time A→B transfer; HIGH enables stored-A→B transfer (from register A).
SBA	B→A data path select	LOW enables real-time B→A transfer; HIGH enables stored-B→A transfer (from register B).
GAB	A→B output enable	LOW enables A→B outputs (A0–A7 drive B0–B7); HIGH places B0–B7 in high-impedance state.
GBA	B→A output enable	LOW enables B→A outputs (B0–B7 drive A0–A7); HIGH places A0–A7 in high-impedance state.
VCC	Positive supply	5 V nominal power rail; decoupling required within 10 mm of pin 24 for stable switching.
GND	Ground reference	Signal and power ground return; must be low-inductance connection shared with VCC decoupling.

Key Features

Feature	Design Value
Independent A/B registers	Enables concurrent storage and transfer: e.g., capture new sensor data on A bus while transmitting prior frame from register B to host processor.
Multiplexed real-time/stored transfer	Per-pin path selection (SAB/SBA) allows dynamic switching between live bus monitoring and buffered command replay without external logic.
TTL-compatible inputs	Eliminates need for input level translators when interfacing with legacy 74LS, 74F, or microcontroller GPIOs operating at 5 V.
3-state outputs with separate enables	GAB and GBA provide independent control over A→B and B→A directions, supporting half-duplex arbitration in shared-bus systems.
SOIC-24 package	Surface-mount form factor with industry-standard footprint (15.5 mm × 7.5 mm), enabling drop-in replacement for through-hole MC74ACT652N in upgraded PCB designs.

Applications

Industrial Backplane Interface	Legacy Microprocessor Bus Expansion
Use Scenario: Interfacing a modern FPGA-based controller to a legacy PLC I/O module using a parallel 16-bit data bus. IC Role / Device Role / Timing Role: Bidirectional registered transceiver managing timing-critical handshaking between mismatched clock domains; registers absorb setup/hold violations during bus arbitration. Use Value: Enables deterministic data capture at 20 MHz using CAB/CBA clocks while isolating FPGA logic from PLC bus noise and skew.	Use Scenario: Adding peripheral memory or I/O to an 8086/8088-based single-board computer with limited address/data bus drive capability. IC Role / Device Role / Timing Role: Octal bus transceiver with register staging, extending bus drive strength and providing latch functionality for wait-state generation. Use Value: Supplies ±24 mA per pin to meet 8086's 2.0 mA minimum input current requirement across all 8 data lines, eliminating need for discrete buffer arrays.
Test Equipment Data Capture	Automated Test Fixture Control
Use Scenario: Capturing parallel digital waveforms from DUT under test and buffering before serial upload to host PC. IC Role / Device Role / Timing Role: Registered input capture device synchronizing asynchronous DUT outputs to internal test controller clock via CAB/CBA. Use Value: Guarantees metastability-free sampling at up to 25 MHz using edge-triggered registers, with real-time pass-through option for debug visibility.	Use Scenario: Controlling 16-channel relay bank and reading status feedback in semiconductor handler equipment. IC Role / Device Role / Timing Role: Dual-directional bus interface translating between isolated control logic (A side) and field-connected relays/sensors (B side). Use Value: Independent GAB/GBA enables safe sequencing: disable B→A reads before asserting A→B commands, preventing bus contention during state transitions.

Industrial Backplane Interface

Legacy Microprocessor Bus Expansion

Use Scenario: Interfacing a modern FPGA-based controller to a legacy PLC I/O module using a parallel 16-bit data bus.

IC Role / Device Role / Timing Role: Bidirectional registered transceiver managing timing-critical handshaking between mismatched clock domains; registers absorb setup/hold violations during bus arbitration.

Use Value: Enables deterministic data capture at 20 MHz using CAB/CBA clocks while isolating FPGA logic from PLC bus noise and skew.

Use Scenario: Adding peripheral memory or I/O to an 8086/8088-based single-board computer with limited address/data bus drive capability.

IC Role / Device Role / Timing Role: Octal bus transceiver with register staging, extending bus drive strength and providing latch functionality for wait-state generation.

Use Value: Supplies ±24 mA per pin to meet 8086's 2.0 mA minimum input current requirement across all 8 data lines, eliminating need for discrete buffer arrays.

Test Equipment Data Capture

Automated Test Fixture Control

Use Scenario: Capturing parallel digital waveforms from DUT under test and buffering before serial upload to host PC.

IC Role / Device Role / Timing Role: Registered input capture device synchronizing asynchronous DUT outputs to internal test controller clock via CAB/CBA.

Use Value: Guarantees metastability-free sampling at up to 25 MHz using edge-triggered registers, with real-time pass-through option for debug visibility.

Use Scenario: Controlling 16-channel relay bank and reading status feedback in semiconductor handler equipment.

IC Role / Device Role / Timing Role: Dual-directional bus interface translating between isolated control logic (A side) and field-connected relays/sensors (B side).

Use Value: Independent GAB/GBA enables safe sequencing: disable B→A reads before asserting A→B commands, preventing bus contention during state transitions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal registered transceiver applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74ACT652N	Identical logic function, pinout, and AC/DC specs; manufactured by Texas Instruments with same 5 V operation and ±24 mA drive.	No functional difference; TI version uses different marking and packaging logistics but meets identical JEDEC standards.	Select SN74ACT652N when sourcing from TI-authorized channels or requiring TI-specific traceability documentation.
MC74ACT652DWG	Same die and functionality as MC74ACT652N, but in SOIC-24 package instead of PDIP-24; identical timing, drive, and voltage specs.	SOIC variant requires PCB redesign for surface-mount assembly but offers better thermal performance and smaller footprint.	Choose MC74ACT652DWG for new designs targeting automated SMT production or space-constrained layouts.

Compared with MC74ACT652N, SN74ACT652N offers identical electrical behavior and drop-in compatibility in through-hole sockets, while MC74ACT652DWG provides the same logic in a surface-mount package-enabling layout optimization without sacrificing timing or drive capability.

Availability

MC74ACT652N is available at Aetrix Electronics and suitable for industrial backplane interfaces, legacy microprocessor bus expansion, test equipment data capture, and automated test fixture control requiring stable component supply across extended product lifecycles.

Supply support for MC74ACT652N includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient silicon solutions for automotive, industrial, cloud, and IoT applications.

The MC74ACT652N belongs to onsemi's legacy 74ACT logic family, engineered for robust 5 V TTL-compatible operation in industrial control, instrumentation, and retro-computing upgrade paths.

FAQ

What is the maximum clock frequency supported by the MC74ACT652N?

The MC74ACT652N does not specify a maximum clock frequency directly, but its propagation delay (tPLH/tPHL) is guaranteed ≤16.5 ns over temperature at 5 V with 50 pF load. This supports reliable operation up to approximately 25 MHz in synchronous bus applications, assuming sufficient setup/hold margins. The minimum clock pulse width is specified as 6.0 ns (tw), confirming viability for >30 MHz edge rates in controlled impedance environments. Always verify timing closure with actual board parasitics and load capacitance.

Does the MC74ACT652N support mixed-voltage operation (e.g., 3.3 V inputs with 5 V supply)?

No, the MC74ACT652N is not rated for mixed-voltage operation. Its input voltage range is specified as 0 V to VCC (4.5–5.5 V), and VIH/VIL thresholds are defined relative to VCC. Applying 3.3 V signals to inputs while VCC = 5 V may result in marginal or undefined logic states, as 3.3 V falls below the guaranteed VIH minimum of 2.0 V only at VCC ≥ 4.5 V - but no DC characterization is provided for VCC = 5 V with VIN = 3.3 V. For 3.3 V ↔ 5 V translation, use a dedicated level-shifter or a 74LVC-series transceiver.

Can the MC74ACT652N be used without connecting both VCC and GND?

No. The MC74ACT652N requires both VCC (pin 24) and GND (pin 12) to be properly connected to function. Leaving either unconnected violates Absolute Maximum Ratings and risks latch-up, excessive ICC, or permanent damage. The device draws quiescent current (ICC ≤ 80 μA) and relies on stable VCC–GND reference for all internal logic, register operation, and output driver biasing. Decoupling capacitors (0.1 μF ceramic) must be placed between VCC and GND within 10 mm of the package.

How does the MC74ACT652N handle bus contention during direction switching?

The MC74ACT652N prevents bus contention through independent 3-state control: GAB disables A→B outputs (B0–B7), and GBA disables B→A outputs (A0–A7). To safely switch direction, assert the new direction's enable (e.g., GAB = LOW) only after first disabling the prior path (e.g., GBA = HIGH). The function table confirms that when both GAB and GBA are HIGH, all outputs enter high-impedance - creating a contention-free "tri-state gap" during reconfiguration. No internal arbitration logic exists; timing must be managed externally.

Is the MC74ACT652N RoHS compliant and lead-free?

Yes, the MC74ACT652N is RoHS compliant and Pb-free. The datasheet explicitly states "These are Pb−Free Devices" and marks packages with 'G' suffix (e.g., MC74ACT652N-G) to indicate lead-free construction. It meets JEDEC J-STD-609A Class 1 marking requirements and has been qualified per IPC/JEDEC J-STD-020 moisture sensitivity level 1 - indicating unlimited floor life at ≤30 °C/60% RH. Full compliance documentation is available from onsemi upon request.

MC74ACT652N Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: 74ACT

Package/Case:: 24-DIP (0.300", 7.62mm)

Packaging:: Tube

Product Status:: Obsolete

Logic Type:: Transceiver, Non-Inverting

Number of Elements:: 1

Number of Bits per Element:: 8

Input Type:: -

Output Type:: 3-State

Current - Output High, Low:: 24mA, 24mA

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Through Hole

Supplier Device Package:: 24-PDIP

MC74ACT652N FAQ

1.How can I place an order for MC74ACT652N through Aetrix?

Please submit a Request for Quotation (RFQ) for MC74ACT652N on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MC74ACT652N reliable?

The price and inventory of MC74ACT652N are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC74ACT652N is usually 5 days.

3.What payment methods are accepted for MC74ACT652N?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC74ACT652N transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MC74ACT652N?

MC74ACT652N orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MC74ACT652N order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MC74ACT652N?

For technical support, including MC74ACT652N datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC74ACT652N requirements.

6.How does Aetrix verify that MC74ACT652N is sourced from the original manufacturer or authorized distributors?

All MC74ACT652N products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC74ACT652N meets industry standards.

7.What is the process for return or replacement of MC74ACT652N?

All MC74ACT652N units undergo pre-shipment inspection (PSI). If there is an issue with MC74ACT652N, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MC74ACT652N part is unused and in its original packaging.

Return procedure for MC74ACT652N:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…