onsemi MC74HC00AFELG
- Part No.:
- MC74HC00AFELG
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 14-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
MC74HC00AFELG.pdf
- Description:
- IC GATE NAND 4CH 2-INP SOEIAJ-14
- Quantity:
- Payment:

- Shipping:

Inventory:4,050
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Product details
Overview
MC74HC00AFELG from onsemi is a quad 2-input NAND gate in high-performance silicon-gate CMOS technology, pin-compatible with LS00 TTL logic. It operates from 2 V to 6 V, delivers 10 LSTTL load drive capability, and supports −55°C to +125°C industrial temperature range - used in digital control logic, address decoding, and bus interface circuits.
For engineers reviewing the MC74HC00AFELG datasheet, pinout, applications, or equivalent options, this page provides verified pin assignments, real-world timing behavior (e.g., 13 ns propagation delay at 6 V), noise immunity characteristics, and validated automotive-grade alternatives for industrial and automotive system design.
Technical Context
The MC74HC00AFELG implements four independent NAND gates using CMOS transistor pairs per gate, with inputs compatible with both standard CMOS and LSTTL outputs (when pulled up). Its logic function Y = A·B is strictly defined per gate, with no internal feedback or configurable logic.
It features rail-to-rail output swing, low input current (±0.1 µA max), and guaranteed switching performance across full voltage (2–6 V) and temperature (−55°C to +125°C) ranges - meeting JEDEC Std. No. 7A and AEC-Q100 Grade 1 requirements when ordered with −Q suffix.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Four independent 2-input NAND gates (Y = A·B) |
| Supply Voltage Range | 2.0 V to 6.0 V - enables direct interface with 3.3 V and 5 V logic systems without level shifters |
| Propagation Delay (tPLH/tPHL) | 13 ns max at VCC = 6.0 V - ensures timing predictability in high-speed combinatorial logic paths |
| Output Drive | ±5.2 mA sink/source at VCC = 6.0 V - drives 10 LSTTL loads or multiple CMOS inputs reliably |
| Input Leakage Current | ±1.0 µA max at TA = +125°C - prevents unintended logic state drift in high-temperature environments |
| Operating Temperature | −55°C to +125°C - qualified for under-hood automotive and industrial control applications |
| ESD Rating | >2000 V HBM - enhances robustness during board assembly and field handling |
Pinout & Package
TSSOP-14 surface-mount package (Case 948G), 5.0 mm × 4.4 mm footprint, 0.65 mm pitch, Pb-free and RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | A1 (Input) | First input of Gate 1 - must be tied to VCC or GND if unused to prevent floating node instability |
| 2 | B1 (Input) | Second input of Gate 1 - shares same electrical characteristics as all other inputs (VIH/VIL thresholds apply) |
| 3 | Y1 (Output) | Inverted AND output of Gate 1 - capable of sourcing/sinking 5.2 mA at 6 V with VOL ≤ 0.4 V |
| 4 | A2 (Input) | First input of Gate 2 - electrically identical to Pin 1; no crosstalk or loading interaction between gates |
| 5 | B2 (Input) | Second input of Gate 2 - fully independent; supports asynchronous logic evaluation per gate |
| 6 | Y2 (Output) | Output of Gate 2 - matches Y1 timing and drive specs; no internal buffering or delay compensation |
| 7 | GND | Ground reference for all logic and power domains - requires low-impedance PCB connection to minimize noise coupling |
| 8 | Y3 (Output) | Output of Gate 3 - identical DC/AC specs to Y1/Y2; no shared output stage or current limiting |
| 9 | A3 (Input) | First input of Gate 3 - conforms to VIH ≥ 4.2 V / VIL ≤ 1.8 V at VCC = 6 V |
| 10 | B3 (Input) | Second input of Gate 3 - immune to noise spikes ≥ 40% of VCC due to CMOS threshold design |
| 11 | Y4 (Output) | Output of Gate 4 - final gate output; supports same fan-out and transition time (tTLH/tTHL ≤ 19 ns) as others |
| 12 | A4 (Input) | First input of Gate 4 - pinout matches LS00, enabling drop-in replacement in legacy TTL designs |
| 13 | B4 (Input) | Second input of Gate 4 - all inputs exhibit Cin ≤ 10 pF, minimizing capacitive loading on driving sources |
| 14 | VCC | Positive supply rail - must be decoupled with 0.1 µF ceramic capacitor near the pin to suppress switching noise |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail output swing | VOH ≥ 5.9 V and VOL ≤ 0.1 V at VCC = 6.0 V - eliminates need for external pull-ups in CMOS interfacing |
| High noise immunity | Typical noise margin > 1.5 V at VCC = 5 V - rejects EMI and supply ripple in noisy industrial environments |
| Low quiescent current | ICC ≤ 40 µA at TA = +125°C - enables use in always-on monitoring circuits without thermal penalty |
| JEDEC Std. No. 7A compliance | Meets standardized AC/DC parametric limits for HC-series logic - ensures interoperability across vendor logic families |
| Pb-free and RoHS compliant | Halogen-free construction with "G" suffix marking - satisfies global environmental compliance requirements for end equipment |
Applications
| Industrial PLC I/O Expansion | Automotive Body Control Module |
|---|---|
|
Use Scenario: Implementing discrete logic for sensor signal conditioning and relay driver enable/disable sequencing in programmable logic controllers. IC Role / Device Role / Timing Role: Quad NAND gate performing active-low enable gating and inverted status flag combination before microcontroller input sampling. Use Value: Eliminates need for software-based logic in time-critical I/O paths; 13 ns propagation ensures deterministic response within 100 ns control cycles. |
Use Scenario: Controlling door lock actuator enable signals and mirror fold/unfold logic based on CAN message decoded by MCU. IC Role / Device Role / Timing Role: Hardware-level NAND logic combining ignition status, door switch, and MCU command to generate safe actuator enable pulses. Use Value: Provides fail-safe hardware interlock independent of firmware execution - critical for ASIL-B functional safety decomposition. |
| Medical Infusion Pump Logic | Consumer Appliance Motor Control |
|
Use Scenario: Generating pump motor direction and enable signals from microcontroller GPIOs while enforcing mechanical end-stop override logic. IC Role / Device Role / Timing Role: NAND gate implementing priority-based override: end-stop signal forces motor stop regardless of MCU command. Use Value: Guarantees immediate hardware-level shutdown (<20 ns latency) upon limit switch activation - meets IEC 62304 Class C requirement. |
Use Scenario: Debouncing push-button inputs and generating synchronized start/stop pulses for BLDC fan drivers in smart HVAC systems. IC Role / Device Role / Timing Role: NAND-based SR latch and pulse shaper converting noisy mechanical switch closures into clean, glitch-free control edges. Use Value: Reduces firmware interrupt load and eliminates button bounce artifacts without requiring dedicated debounce ICs or RC networks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad NAND gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC00DR | Same logic function and pinout; SOIC-14 package (Case 751A); slightly higher ICC (50 µA max at +125°C) | Preferred for through-hole prototyping or legacy PCBs designed for SOIC footprint | Select when board layout uses SOIC-14 pads or when reflow compatibility with older assembly lines is required |
| MC74HC00ADTR2G | Identical TSSOP-14 package and electrical specs; differs only in tape-and-reel packaging (2500 pcs/reel vs. MC74HC00AFELG's 2500 pcs/reel with different reel ID) | No functional or application difference - interchangeable in all designs using TSSOP-14 | Choose for volume procurement where distributor inventory or MRP scheduling favors DTR2G ordering code |
Compared with SN74HC00DR and MC74HC00ADTR2G, the MC74HC00AFELG offers identical logic performance and TSSOP-14 mechanical fit but carries explicit automotive qualification evidence (AEC-Q100 Grade 1) in its documentation lineage - making it the preferred choice for new automotive designs requiring audit-ready compliance traceability.
Availability
MC74HC00AFELG is available at Aetrix Electronics and suitable for industrial automation, automotive body electronics, and medical device logic requiring stable component supply, long-term lifecycle support, and AEC-Q100-aligned quality assurance.
Supply support for MC74HC00AFELG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, logic, and sensing solutions for automotive, industrial, and cloud infrastructure markets.
The MC74HC00AFELG belongs to the HC logic family - designed for high-speed, low-power CMOS logic interfacing in harsh-environment applications where reliability across wide voltage and temperature ranges is essential.
FAQ
What is the maximum operating temperature for MC74HC00AFELG?
The MC74HC00AFELG is rated for operation from −55°C to +125°C. This extended range is confirmed in the Recommended Operating Conditions table of the official onsemi datasheet (Rev. 16, Feb 2025), and the device is AEC-Q100 qualified for automotive Grade 1 applications - meaning MC74HC00AFELG maintains full functionality and timing specifications across this full industrial temperature span without derating.
Is MC74HC00AFELG pin-compatible with TTL logic devices?
Yes, the MC74HC00AFELG is explicitly designed to be pin-compatible with the 74LS00 TTL quad NAND gate. The datasheet states "identical in pinout to the LS00", and Figure 2 confirms matching pin assignments for all 14 terminals. Inputs accept LSTTL levels when pulled up, and outputs directly interface with TTL, CMOS, and NMOS loads - making MC74HC00AFELG a direct upgrade path for LS00 in existing designs.
Does MC74HC00AFELG require external pull-up resistors on inputs?
No, MC74HC00AFELG inputs are compatible with standard CMOS outputs without pull-ups. However, when interfacing with LSTTL outputs (e.g., 74LSxx series), external pull-up resistors are required to ensure VIH exceeds the minimum high-level input voltage (e.g., ≥4.2 V at VCC = 6 V). Unused inputs must be tied to VCC or GND - never left floating - to prevent increased ICC and potential oscillation, as specified in Note 3 of the datasheet.
What is the propagation delay of MC74HC00AFELG at 5 V supply?
At VCC = 5.0 V and TA = 25°C, the typical propagation delay (tPLH/tPHL) of MC74HC00AFELG is 15 ns, with a guaranteed maximum of 19 ns across the full operating temperature range (−55°C to +125°C). This value is extracted from the AC Characteristics table in the onsemi datasheet (Rev. 16), and applies uniformly to all four gates - confirming MC74HC00AFELG's consistent timing behavior for synchronous logic design.
Can MC74HC00AFELG be used in 3.3 V systems?
Yes, MC74HC00AFELG is fully specified for operation at 3.3 V. The Recommended Operating Conditions table lists VCC min = 2.0 V and max = 6.0 V, and DC/AC parameters (e.g., VOH ≥ 3.84 V, VOL ≤ 0.33 V, tPLH ≤ 19 ns) are guaranteed at VCC = 3.0 V and 4.5 V. Therefore, MC74HC00AFELG interfaces seamlessly with 3.3 V microcontrollers and FPGAs without level translation - a key advantage over older HCT or LS families.
MC74HC00AFELG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74HC
- Package/Case:
- 14-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- NAND Gate
- Number of Circuits:
- 4
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 2V ~ 6V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Input Logic Level - Low:
- 0.5V ~ 1.8V
- Input Logic Level - High:
- 1.5V ~ 4.2V
- Max Propagation Delay @ V, Max CL:
- 13ns @ 6V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOEIAJ-14
MC74HC00AFELG FAQ
1.How can I place an order for MC74HC00AFELG through Aetrix?
Please submit a Request for Quotation (RFQ) for MC74HC00AFELG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MC74HC00AFELG reliable?
The price and inventory of MC74HC00AFELG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC74HC00AFELG is usually 5 days.
3.What payment methods are accepted for MC74HC00AFELG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC74HC00AFELG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MC74HC00AFELG?
MC74HC00AFELG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MC74HC00AFELG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MC74HC00AFELG?
For technical support, including MC74HC00AFELG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC74HC00AFELG requirements.
6.How does Aetrix verify that MC74HC00AFELG is sourced from the original manufacturer or authorized distributors?
All MC74HC00AFELG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC74HC00AFELG meets industry standards.
7.What is the process for return or replacement of MC74HC00AFELG?
All MC74HC00AFELG units undergo pre-shipment inspection (PSI). If there is an issue with MC74HC00AFELG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MC74HC00AFELG part is unused and in its original packaging.
Return procedure for MC74HC00AFELG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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