onsemi MC74HC32ADTR2
- Part No.:
- MC74HC32ADTR2
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
MC74HC32ADTR2.pdf
- Description:
- IC GATE OR 4CH 2-INP 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,871
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Product details
Overview
MC74HC32ADTR2 from onsemi is a quad 2-input OR gate in TSSOP-14 package, operating across 2.0–6.0 V supply, delivering 10 LSTTL load drive capability with propagation delay as low as 13 ns at 6.0 V, used in digital logic interfacing and level translation within industrial control and automotive subsystems.
For engineers reviewing the MC74HC32ADTR2 datasheet, pinout, applications, or equivalent options, key selection criteria include supply voltage range compatibility (2.0–6.0 V), guaranteed propagation delay at temperature extremes (≤110 ns at −55°C to +125°C), input/output voltage tolerance (0 to VCC), and AEC-Q100 qualification for automotive use.
Technical Context
The MC74HC32ADTR2 implements four independent OR logic functions (Y = A + B) using high-performance silicon-gate CMOS technology. Its inputs are compatible with standard CMOS outputs and-when pulled up-are compatible with LSTTL outputs, enabling mixed-logic-family interfacing without level shifters.
It features rail-to-rail output swing, low input current (±0.1 µA typical), and high noise immunity inherent to CMOS design. The device supports operation from −55°C to +125°C and meets JEDEC Std. No. 7A, with ESD robustness >2000 V HBM.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Quad 2-input OR gate (Y = A + B), fully independent channels |
| Supply Voltage Range | 2.0 V to 6.0 V - enables direct interface with 3.3 V and 5 V systems |
| Propagation Delay | 13 ns max at VCC = 6.0 V, TA ≤ 25°C - ensures timing-critical combinational logic integrity |
| Output Drive | 10 LSTTL loads - sufficient to drive legacy TTL inputs without buffering |
| Operating Temperature | −55°C to +125°C - qualified for under-hood automotive and industrial environments |
| Input Leakage Current | ±0.1 µA max at VCC = 6.0 V - minimizes static power and signal integrity impact in high-impedance nodes |
| ESD Rating | >2000 V HBM - provides robust handling during board assembly and field service |
Pinout & Package
TSSOP-14 package (Case 948G), 4.9 mm × 4.4 mm × 1.2 mm body, 0.65 mm pitch, Pb-free, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | A1 (Input) | First input of Gate 1 - must be tied to valid logic level if unused |
| 2 | B1 (Input) | Second input of Gate 1 - forms OR function Y1 = A1 + B1 |
| 3 | Y1 (Output) | Output of Gate 1 - rail-to-rail CMOS swing, drives up to 10 LSTTL loads |
| 4 | A2 (Input) | First input of Gate 2 - electrically isolated from other gates |
| 5 | B2 (Input) | Second input of Gate 2 - forms OR function Y2 = A2 + B2 |
| 6 | Y2 (Output) | Output of Gate 2 - no internal loading between gates |
| 7 | GND | Ground reference for all logic and power - mandatory connection for stable operation |
| 8 | Y3 (Output) | Output of Gate 3 - identical electrical characteristics to Y1/Y2/Y4 |
| 9 | A3 (Input) | First input of Gate 3 - shares same VCC/GND domain but no internal coupling |
| 10 | B3 (Input) | Second input of Gate 3 - forms OR function Y3 = A3 + B3 |
| 11 | Y4 (Output) | Output of Gate 4 - fully buffered, no fanout limitation beyond 10 LSTTL |
| 12 | A4 (Input) | First input of Gate 4 - supports independent logic path routing |
| 13 | B4 (Input) | Second input of Gate 4 - forms OR function Y4 = A4 + B4 |
| 14 | VCC | Positive supply rail - decoupling capacitor (0.1 µF) required near pin for noise suppression |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail CMOS output swing | VOH ≥ 5.9 V and VOL ≤ 0.1 V at VCC = 6.0 V - eliminates need for external level translators when interfacing with 5 V logic |
| LSTTL-compatible input thresholds | VIH = 4.2 V, VIL = 1.8 V at VCC = 6.0 V - ensures reliable recognition of TTL-high/low signals with pull-up resistors |
| Low quiescent supply current | ICC ≤ 40 µA at VCC = 6.0 V, TA = +125°C - supports always-on logic in power-constrained embedded systems |
| High noise immunity | CMOS input structure with >40% VCC noise margin - suppresses false triggering in electrically noisy industrial environments |
| AEC-Q100 qualified | Automotive-grade reliability with PPAP capability - validated for use in engine control, body electronics, and ADAS subsystems |
Applications
| Industrial PLC I/O Expansion | Automotive Body Control Module |
|---|---|
Use Scenario: Adding discrete OR logic to merge multiple sensor fault flags into a single diagnostic alert line in a programmable logic controller. IC Role / Device Role / Timing Role: Combinational logic gate aggregating four independent status inputs into four parallel OR outputs with sub-15 ns propagation. Use Value: Eliminates microcontroller GPIO overhead and software polling latency while maintaining deterministic response time under all temperature conditions. |
Use Scenario: Implementing door lock status arbitration where multiple switches (driver, passenger, rear) must OR together to activate central lock actuation. IC Role / Device Role / Timing Role: Hardware-level OR combiner ensuring immediate mechanical response without MCU intervention or firmware delay. Use Value: Meets ASIL-B functional safety timing requirements by guaranteeing <110 ns worst-case delay across −40°C to +125°C ambient. |
| Medical Infusion Pump Logic Interface | Test Equipment Signal Conditioning |
Use Scenario: Combining "motor stall", "occlusion detected", and "door open" alarms into a unified hardware shutdown signal for fail-safe pump halt. IC Role / Device Role / Timing Role: Safety-critical combinational gate providing immediate hardware-level fault aggregation independent of main processor. Use Value: Supports IEC 62304 Class C software safety architecture by offloading time-critical fault logic to deterministic, non-programmable hardware. |
Use Scenario: Converting multiple TTL-compatible trigger sources (oscilloscope, function generator, DUT) into a single standardized CMOS-level enable signal for test fixture sequencing. IC Role / Device Role / Timing Role: Level-shifting OR gate accepting mixed-voltage inputs and delivering clean 3.3 V/5 V CMOS outputs. Use Value: Enables plug-and-play interoperability between legacy 5 V instruments and modern 3.3 V FPGA-based controllers without discrete resistor networks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 2-input OR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC32PWR | TSSOP-14, identical logic and AC specs, but not AEC-Q100 qualified; max TA = +85°C commercial grade | Suitable only for non-automotive, non-industrial environments with controlled temperature | Select when cost sensitivity outweighs automotive qualification and extended temperature support |
| MC74HC32ADR2G | SOIC-14 package (7.5 mm × 5.0 mm), same electrical specs and AEC-Q100 qualification, but larger footprint and higher thermal resistance (116°C/W vs 150°C/W) | Preferred for through-hole prototyping or legacy PCBs with SOIC footprints | Select when board space permits larger package or reflow compatibility with existing SOIC assembly lines is required |
Compared with SN74HC32PWR and MC74HC32ADR2G, the MC74HC32ADTR2 uniquely combines AEC-Q100 qualification, −55°C to +125°C operation, and compact TSSOP-14 packaging - making it the only choice for space-constrained automotive modules requiring full temperature-range reliability.
Availability
MC74HC32ADTR2 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, medical infusion pump logic interfaces, and test equipment signal conditioning requiring stable component supply across extended temperature ranges and automotive-grade traceability.
Supply support for MC74HC32ADTR2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, logic, and sensing solutions for automotive, industrial, and cloud infrastructure markets.
The MC74HC32ADTR2 belongs to the 74HC logic family, designed for high-speed, low-power CMOS digital interfacing in harsh-environment applications where reliability, wide supply range, and mixed-logic compatibility are critical.
FAQ
What is the maximum operating temperature range for the MC74HC32ADTR2?
The MC74HC32ADTR2 is rated for operation from −55°C to +125°C, verified per JEDEC standards and confirmed in the onsemi datasheet Section 3 (Recommended Operating Conditions). This full industrial-plus-automotive range is enabled by its AEC-Q100 qualification and silicon-gate CMOS process, making MC74HC32ADTR2 suitable for under-hood and enclosed industrial environments where thermal cycling exceeds commercial-grade limits.
Does the MC74HC32ADTR2 support 3.3 V logic systems?
Yes, the MC74HC32ADTR2 operates reliably at 3.3 V supply (within its 2.0–6.0 V range), with guaranteed VIH = 2.10 V and VIL = 0.90 V at VCC = 3.0 V - comfortably accommodating standard 3.3 V CMOS logic levels. Its output VOH ≥ 2.48 V and VOL ≤ 0.26 V at 3.0 V further ensure interoperability with 3.3 V receivers, confirming MC74HC32ADTR2 as a drop-in solution for mixed-voltage digital subsystems.
Is the MC74HC32ADTR2 pin-compatible with the older 74LS32?
Yes, the MC74HC32ADTR2 is explicitly designed to be pinout-identical to the 74LS32, as stated in the onsemi datasheet: "The MC74HC32A/MC74HCT32A is identical in pinout to the LS32." This allows direct replacement in legacy designs, though MC74HC32ADTR2 requires pull-up resistors on inputs when interfacing with LSTTL outputs due to its CMOS input structure.
What is the propagation delay of the MC74HC32ADTR2 at 5 V supply?
At VCC = 5.0 V and TA ≤ 25°C, the MC74HC32ADTR2 exhibits a maximum propagation delay (tPLH/tPHL) of 16 ns, per the AC Characteristics table in the onsemi datasheet. At elevated temperatures (+125°C), this increases to 19 ns, ensuring predictable timing behavior across the full operating range - a key specification for MC74HC32ADTR2 in synchronous digital control paths.
Can unused inputs on the MC74HC32ADTR2 be left floating?
No - unused inputs on the MC74HC32ADTR2 must be tied to a valid logic level (VCC or GND), as explicitly required in the datasheet's Recommended Operating Conditions footnote: "Unused inputs must always be tied to an appropriate logic voltage level." Floating inputs risk oscillation, increased power consumption, and potential latch-up, compromising MC74HC32ADTR2 reliability in production systems.
MC74HC32ADTR2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74HC
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- OR Gate
- Number of Circuits:
- 4
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 2V ~ 6V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Input Logic Level - Low:
- 0.5V ~ 1.8V
- Input Logic Level - High:
- 1.5V ~ 4.2V
- Max Propagation Delay @ V, Max CL:
- 13ns @ 6V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
MC74HC32ADTR2 FAQ
1.How can I place an order for MC74HC32ADTR2 through Aetrix?
Please submit a Request for Quotation (RFQ) for MC74HC32ADTR2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MC74HC32ADTR2 reliable?
The price and inventory of MC74HC32ADTR2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC74HC32ADTR2 is usually 5 days.
3.What payment methods are accepted for MC74HC32ADTR2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC74HC32ADTR2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MC74HC32ADTR2?
MC74HC32ADTR2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MC74HC32ADTR2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MC74HC32ADTR2?
For technical support, including MC74HC32ADTR2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC74HC32ADTR2 requirements.
6.How does Aetrix verify that MC74HC32ADTR2 is sourced from the original manufacturer or authorized distributors?
All MC74HC32ADTR2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC74HC32ADTR2 meets industry standards.
7.What is the process for return or replacement of MC74HC32ADTR2?
All MC74HC32ADTR2 units undergo pre-shipment inspection (PSI). If there is an issue with MC74HC32ADTR2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MC74HC32ADTR2 part is unused and in its original packaging.
Return procedure for MC74HC32ADTR2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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