onsemi MC74HC367ADR2G
- Part No.:
- MC74HC367ADR2G
- Manufacturer:
- onsemi
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
MC74HC367ADR2G.pdf
- Description:
- IC BUFFER NON-INVERT 6V 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,450
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Product details
Overview
MC74HC367ADR2G from onsemi is a hex 3-state noninverting buffer IC with separate 2-bit and 4-bit sections, each controlled by its own active-low output enable. It operates from 2.0 V to 6.0 V, delivers ±25 mA output drive per pin, and supports LSTTL/CMOS/NMOS/TTL interfacing in industrial control and data bus isolation applications.
For engineers reviewing the MC74HC367ADR2G datasheet, pinout, applications, or equivalent options, key selection criteria include dual-section enable control, high-noise-immunity CMOS logic, 125°C operating temperature, SOIC-16 Pb-free packaging, and compatibility with legacy LS367 layouts.
Technical Context
The MC74HC367ADR2G implements six independent noninverting buffers partitioned into two groups: A0–A1/Y0–Y1 (2-bit section) and A2–A5/Y2–Y5 (4-bit section), each with dedicated active-low output enables (OE1, OE2). Its silicon-gate CMOS architecture ensures low input current (±0.1 µA at VCC = 6.0 V) and high noise immunity across −55°C to +125°C.
Propagation delays are voltage-dependent: tPLH/tPHL ≤ 20 ns at VCC = 6.0 V (CL = 50 pF); enable-to-output delays (tPLZ/tPHZ) reach 30 ns under same conditions. Input capacitance is capped at 10 pF, and three-state output capacitance at 15 pF - critical for high-speed bus loading control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 6.0 V - supports mixed-voltage system interfacing (e.g., 3.3 V logic driving 5 V bus) |
| Output Drive | ±25 mA per pin - drives up to 15 LSTTL loads without external buffering |
| Propagation Delay (A→Y) | ≤20 ns at VCC = 6.0 V - enables reliable operation in 25 MHz+ digital control paths |
| Operating Temperature | −55°C to +125°C - qualified for under-hood automotive and industrial motor control environments |
| Input Leakage Current | ±0.1 µA max at VCC = 6.0 V - minimizes power loss in battery-backed or low-quiescent systems |
| Three-State Leakage | ±0.5 µA max at VCC = 6.0 V - ensures clean bus contention avoidance during high-impedance state |
| Power Dissipation Cap | 500 mW (SOIC-16) - allows sustained operation at full drive without thermal derating in standard PCBs |
Pinout & Package
MC74HC367ADR2G is packaged in Pb-free SOIC-16 (Case 751B), 9.90 mm × 3.90 mm × 1.37 mm body, 1.27 mm pitch. Pin 1 is index-marked; Pin 8 = GND; Pin 16 = VCC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | OE1 (Output Enable 1) | Active-low enable for Y0, Y1 - controls 2-bit section independently of 4-bit section |
| 2 | A0 | Input for noninverting buffer Y0 - direct logic pass-through with no inversion |
| 3 | Y0 | Noninverting output for A0 - high-impedance when OE1 = high |
| 4 | A1 | Input for noninverting buffer Y1 |
| 5 | Y1 | Noninverting output for A1 |
| 6 | OE2 (Output Enable 2) | Active-low enable for Y2–Y5 - isolates 4-bit section without affecting Y0/Y1 |
| 7 | A2 | Input for Y2 |
| 8 | GND | Ground reference for all I/O and supply |
| 9 | Y2 | Noninverting output for A2 |
| 10 | A3 | Input for Y3 |
| 11 | Y3 | Noninverting output for A3 |
| 12 | A4 | Input for Y4 |
| 13 | Y4 | Noninverting output for A4 |
| 14 | A5 | Input for Y5 |
| 15 | Y5 | Noninverting output for A5 |
| 16 | VCC | Positive supply rail - must be decoupled locally to suppress switching noise |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent output enables | OE1 and OE2 allow selective activation of 2-bit and 4-bit sections - enables partial bus gating without global disable |
| High noise immunity | CMOS input thresholds (VIH ≥ 3.15 V @ VCC = 4.5 V) reject >1.35 V noise spikes - improves reliability in EMI-prone motor drives |
| LSTTL load compatibility | 15 LSTTL loads per output - eliminates need for level-shifting buffers when interfacing with legacy TTL subsystems |
| Pb-free SOIC-16 package | RoHS-compliant, industry-standard footprint - drop-in replacement for MC74HC367ADG and LS367 designs |
| Wide temperature range | −55°C to +125°C operation - validated for engine control units and industrial PLC backplanes |
Applications
| Industrial Data Bus Isolation | Automotive Sensor Interface |
|---|---|
|
Use Scenario: Isolating microcontroller GPIOs from noisy CAN/LIN transceiver buses in programmable logic controllers. IC Role / Device Role / Timing Role: Noninverting buffer with independent OE control - prevents bus contention during firmware updates or fault recovery. Use Value: Dual OE pins allow real-time segmentation: 2-bit section handles status LEDs while 4-bit section gates sensor data lines - no software reconfiguration needed. |
Use Scenario: Level-shifting and buffering analog-to-digital converter (ADC) outputs in engine control modules operating at 5 V. IC Role / Device Role / Timing Role: Signal integrity conditioner - converts high-impedance ADC outputs to robust CMOS drive capability before routing to MCU inputs. Use Value: ±25 mA drive and 10 pF input capacitance minimize settling time distortion - preserves 12-bit ADC accuracy under 125°C ambient. |
| Legacy TTL System Upgrade | Programmable Logic Expansion |
|
Use Scenario: Replacing obsolete 74LS367 in avionics maintenance test equipment requiring extended temperature support. IC Role / Device Role / Timing Role: Pin-compatible CMOS upgrade - retains identical pinout and logic function while reducing power and improving noise margin. Use Value: 2.0–6.0 V supply range allows direct integration into existing 5 V rails; 0.1 µA input leakage cuts standby current by >95% vs. LS family. |
Use Scenario: Expanding I/O count in FPGA-based industrial motion controllers using discrete logic for address/data demultiplexing. IC Role / Device Role / Timing Role: Bus driver for parallel configuration registers - provides clean, slew-controlled signals to FPGA configuration pins. Use Value: 20 ns propagation delay at 6 V ensures setup/hold timing closure for 25 MHz FPGA clock domains; 15 pF three-state capacitance prevents signal ringback. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex noninverting buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC367N | Same logic function and pinout; rated only to +70°C (commercial temp), higher ICC (max 80 µA vs. 4 µA) | Not suitable for under-hood or industrial environments requiring >85°C operation | Select MC74HC367ADR2G for extended temperature or ultra-low quiescent current needs |
| 74VHC367M | Higher speed (tPLH ≤ 10.5 ns @ VCC = 5 V), but narrower VCC range (2.0–5.5 V) and no −55°C rating | Limited to consumer-grade or lab equipment where 125°C operation is unnecessary | Choose MC74HC367ADR2G when full industrial temperature range and 6.0 V tolerance are required |
Compared with SN74HC367N and 74VHC367M, MC74HC367ADR2G uniquely combines −55°C to +125°C operation, 6.0 V absolute maximum supply, and 4 µA typical ICC - making it the only option qualified for harsh-environment automotive and industrial control without derating.
Availability
MC74HC367ADR2G is available at Aetrix Electronics and suitable for industrial automation, automotive engine management, and legacy system upgrades requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.
Supply support for MC74HC367ADR2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient, high-reliability components for automotive, industrial, and cloud infrastructure markets.
The MC74HC367ADR2G belongs to onsemi's HC logic family - designed for robust, low-power digital interfacing in mission-critical systems where noise immunity, wide voltage operation, and extended temperature performance are mandatory.
FAQ
What is the maximum supply voltage rating for MC74HC367ADR2G?
The MC74HC367ADR2G has an absolute maximum DC supply voltage (VCC) of +7.0 V referenced to GND. However, the recommended operating range is 2.0 V to 6.0 V. Operating continuously above 6.0 V risks exceeding internal oxide breakdown limits and is not guaranteed for reliability or parametric performance - always maintain VCC ≤ 6.0 V in production designs using MC74HC367ADR2G.
Does MC74HC367ADR2G support mixed-voltage interfacing between 3.3 V and 5 V systems?
Yes, MC74HC367ADR2G supports mixed-voltage interfacing: its input thresholds scale with VCC (e.g., VIH ≥ 3.15 V at VCC = 4.5 V), and outputs swing rail-to-rail. When powered at 5 V, it reliably accepts 3.3 V logic-high inputs (exceeding VIH min), and when powered at 3.3 V, its outputs meet 3.3 V logic-high requirements - enabling bidirectional level translation in MC74HC367ADR2G-based bus interfaces.
How does the dual output-enable architecture of MC74HC367ADR2G improve system design flexibility?
The MC74HC367ADR2G features two independent active-low output enables (OE1 for Y0/Y1; OE2 for Y2–Y5), allowing granular control over signal routing. This enables partial bus isolation - for example, holding sensor data lines (Y2–Y5) in high-Z while keeping status indicators (Y0/Y1) active - without software intervention or additional logic. That architectural separation directly reduces complexity in MC74HC367ADR2G-based industrial I/O modules.
Is MC74HC367ADR2G pin-compatible with the older 74LS367 device?
Yes, MC74HC367ADR2G is explicitly designed as a pinout-identical replacement for the 74LS367. The datasheet confirms identical pin assignment, logic function, and functional block diagram. However, MC74HC367ADR2G requires pullup resistors for LSTTL input compatibility and operates across 2.0–6.0 V - unlike the LS367's fixed 5 V requirement - so MC74HC367ADR2G retains mechanical and electrical layout compatibility while extending voltage and temperature capability.
What is the typical quiescent supply current (ICC) of MC74HC367ADR2G at 25°C and VCC = 6.0 V?
The typical quiescent supply current (ICC) for MC74HC367ADR2G is 4 µA at 25°C and VCC = 6.0 V, with a maximum guaranteed limit of 160 µA across the full −55°C to +125°C range. This ultra-low ICC enables use in always-on subsystems such as automotive wake-up circuits or battery-backed industrial monitors - a key differentiator versus LS or ALS logic families, where ICC typically exceeds 10 mA.
MC74HC367ADR2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74HC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 7.8mA, 7.8mA
- Voltage - Supply:
- 2V ~ 6V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
MC74HC367ADR2G FAQ
1.How can I place an order for MC74HC367ADR2G through Aetrix?
Please submit a Request for Quotation (RFQ) for MC74HC367ADR2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MC74HC367ADR2G reliable?
The price and inventory of MC74HC367ADR2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC74HC367ADR2G is usually 5 days.
3.What payment methods are accepted for MC74HC367ADR2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC74HC367ADR2G transactions.
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4.How is shipping managed for MC74HC367ADR2G?
MC74HC367ADR2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MC74HC367ADR2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MC74HC367ADR2G?
For technical support, including MC74HC367ADR2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC74HC367ADR2G requirements.
6.How does Aetrix verify that MC74HC367ADR2G is sourced from the original manufacturer or authorized distributors?
All MC74HC367ADR2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC74HC367ADR2G meets industry standards.
7.What is the process for return or replacement of MC74HC367ADR2G?
All MC74HC367ADR2G units undergo pre-shipment inspection (PSI). If there is an issue with MC74HC367ADR2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MC74HC367ADR2G part is unused and in its original packaging.
Return procedure for MC74HC367ADR2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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