Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

onsemi MC74LCX04DTR2

Name: MC74LCX04DTR2
Brand: onsemi
SKU: MC74LCX04DTR2
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: MC74LCX04DTR2

Manufacturer:: onsemi

Category:: Gates and Inverters

Package:: 14-TSSOP (0.173", 4.40mm Width)

Datasheet:: MC74LCX04DTR2.pdf

Description:: IC INVERTER 6CH 1-INP 14TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,447

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

MC74LCX04DTR2 from onsemi is a low-voltage CMOS hex inverter with 5 V-tolerant inputs, operating from 1.65 V to 5.5 V supply. It delivers balanced ±24 mA output drive at 3.0 V, features near-zero static supply current (10 µA), and supports automotive-grade AEC-Q100 qualification. It is used in level-shifting logic interfaces between 3.3 V/2.5 V systems and legacy 5 V TTL buses.

For engineers reviewing the MC74LCX04DTR2 datasheet, pinout, applications, or equivalent options, key selection factors include 5 V input tolerance under sub-5 V V_CC, propagation delay ≤4.2 ns (at 4.5–5.5 V), LVTTL/LVCMOS compatibility, and TSSOP-14 packaging for space-constrained PCB layouts.

Technical Context

The MC74LCX04DTR2 implements six independent CMOS inverter stages in a single monolithic IC, each with high-impedance TTL-compatible inputs and rail-to-rail push-pull outputs. Its input structure allows safe interfacing with 5 V logic while powered from as low as 1.65 V, eliminating external level shifters in mixed-voltage systems.

It exhibits latchup immunity exceeding 100 mA and ESD robustness >2000 V HBM. The device operates across −40 °C to +125 °C, with propagation delays specified from 1.5 ns (at 2.3–3.6 V) to 4.2 ns (at 4.5–5.5 V), and maintains stable VIH/VIL thresholds across V_CC ranges per JEDEC JESD8-5A.

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	1.65 V to 5.5 V - Enables direct operation in 1.8 V, 2.5 V, 3.3 V, and 5 V domains without voltage translation.
Input Voltage Tolerance	−0.5 V to +6.5 V - Allows 5 V TTL signals to drive inputs safely even when V_CC = 3.3 V or lower.
Output Drive @ 3.0 V	±24 mA - Sufficient to drive multiple LVTTL loads or moderate capacitive loads (e.g., 50 pF) with fast edge rates.
Propagation Delay	≤4.2 ns max (4.5–5.5 V) - Supports >100 MHz toggle rates in critical timing paths.
Quiescent Current	10 µA max - Minimizes standby power in battery-backed or always-on subsystems.
Operating Temperature	−40 °C to +125 °C - Validated for under-hood automotive and industrial control environments.
ESD Rating	Human Body Model >2000 V - Reduces risk of field failure during handling and assembly.

Pinout & Package

TSSOP-14 package (Case 948G), 4.9 mm × 4.4 mm footprint, 0.65 mm pitch, lead-free (Pb-free) construction.

Pin/Terminal	Circuit Role	Design Meaning
1	A0	Inverter input channel 0 - High-impedance, 5 V-tolerant CMOS input.
2	O0	Inverter output channel 0 - Push-pull output with ±24 mA drive capability at 3.0 V.
3	A1	Inverter input channel 1 - Electrically identical to A0; no internal coupling.
4	O1	Inverter output channel 1 - Independent output stage; supports simultaneous switching.
5	A2	Inverter input channel 2 - Matches A0/A1 electrical specs and timing behavior.
6	O2	Inverter output channel 2 - Fully buffered; no fanout limitation beyond I_OH/I_OL ratings.
7	GND	Ground reference - All input thresholds and output levels referenced to this pin.
8	O3	Inverter output channel 3 - Same AC/DC characteristics as O0–O2.
9	A3	Inverter input channel 3 - Supports same VIH/VIL thresholds across full V_CC range.
10	O4	Inverter output channel 4 - Verified skew ≤1.0 ns (t_OSHL/t_OSLH) between outputs at 3.0–3.6 V.
11	A4	Inverter input channel 4 - Compatible with LVTTL and LVCMOS logic families.
12	O5	Inverter output channel 5 - Final output; shares same thermal resistance (θ_JA = 150 °C/W).
13	A5	Inverter input channel 5 - Unused inputs must be tied to V_CC or GND per datasheet guidance.
14	V_CC	Positive supply - Decoupling capacitor (0.1 µF ceramic) required within 10 mm of this pin.

Key Features

Feature	Design Value
5 V-tolerant inputs	Enables direct connection to 5 V TTL outputs while V_CC = 1.65–4.9 V, eliminating discrete level shifters.
Balanced ±24 mA drive @ 3.0 V	Supports driving 10+ LVTTL loads or 50 pF bus capacitance with <5 ns propagation delay and minimal ground bounce.
10 µA max ICC quiescent current	Reduces system-level standby power by >95% vs. older 74HC-series inverters, critical for energy-sensitive applications.
AEC-Q100 qualified (−Q suffix)	Validated for automotive use including PPAP compliance, extended temperature operation, and stress testing per Q100 Rev G.
Latchup immunity >100 mA	Prevents destructive latchup events during transient overvoltage or hot-swap conditions in industrial backplanes.

Applications

Automotive Body Control Module	Industrial PLC I/O Interface
Use Scenario: Level-shifting sensor signal conditioning in door module ECUs where 5 V Hall-effect sensors interface with 3.3 V microcontroller GPIO. IC Role / Device Role / Timing Role: Signal inversion and voltage domain bridging between legacy 5 V analog front-end and low-power 3.3 V MCU. Use Value: Eliminates need for discrete MOSFET translators; reduces BOM count and layout area while maintaining AEC-Q100 compliance.	Use Scenario: Driving optocoupler inputs in isolated digital output cards where 24 V PLC logic must be inverted and translated to 3.3 V FPGA control lines. IC Role / Device Role / Timing Role: Logic-level inversion and 5 V-tolerant input buffering for robust noise immunity in electrically noisy factory environments. Use Value: Withstands 6.5 V transients on inputs and delivers clean 3.3 V logic edges with <4.2 ns delay, improving real-time response.
Medical Patient Monitor Data Bus	Consumer IoT Hub Power Sequencing
Use Scenario: Inverting reset signals between 5 V power management ICs and 1.8 V SoC subsystems in portable diagnostic devices. IC Role / Device Role / Timing Role: Glue logic for synchronized power-up sequencing across mixed-voltage domains with guaranteed monotonic transitions. Use Value: Near-zero ICC ensures negligible impact on battery runtime; 125 °C rating supports sealed enclosure thermal profiles.	Use Scenario: Controlling enable/disable states of multiple 3.3 V peripherals (Wi-Fi, BLE, sensors) using inverted GPIO from a 5 V host MCU. IC Role / Device Role / Timing Role: Low-power active-high to active-low signal conversion with fast turn-on/turn-off for dynamic power gating. Use Value: 24 mA sink/source capability drives multiple MOSFET gates directly; 10 µA ICC extends sleep-mode battery life.

Automotive Body Control Module

Industrial PLC I/O Interface

Use Scenario: Level-shifting sensor signal conditioning in door module ECUs where 5 V Hall-effect sensors interface with 3.3 V microcontroller GPIO.

IC Role / Device Role / Timing Role: Signal inversion and voltage domain bridging between legacy 5 V analog front-end and low-power 3.3 V MCU.

Use Value: Eliminates need for discrete MOSFET translators; reduces BOM count and layout area while maintaining AEC-Q100 compliance.

Use Scenario: Driving optocoupler inputs in isolated digital output cards where 24 V PLC logic must be inverted and translated to 3.3 V FPGA control lines.

IC Role / Device Role / Timing Role: Logic-level inversion and 5 V-tolerant input buffering for robust noise immunity in electrically noisy factory environments.

Use Value: Withstands 6.5 V transients on inputs and delivers clean 3.3 V logic edges with <4.2 ns delay, improving real-time response.

Medical Patient Monitor Data Bus

Consumer IoT Hub Power Sequencing

Use Scenario: Inverting reset signals between 5 V power management ICs and 1.8 V SoC subsystems in portable diagnostic devices.

IC Role / Device Role / Timing Role: Glue logic for synchronized power-up sequencing across mixed-voltage domains with guaranteed monotonic transitions.

Use Value: Near-zero ICC ensures negligible impact on battery runtime; 125 °C rating supports sealed enclosure thermal profiles.

Use Scenario: Controlling enable/disable states of multiple 3.3 V peripherals (Wi-Fi, BLE, sensors) using inverted GPIO from a 5 V host MCU.

IC Role / Device Role / Timing Role: Low-power active-high to active-low signal conversion with fast turn-on/turn-off for dynamic power gating.

Use Value: 24 mA sink/source capability drives multiple MOSFET gates directly; 10 µA ICC extends sleep-mode battery life.

Equivalent & Alternatives

The following parts are listed as comparable options for similar hex inverter applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC04APWR	Same 1.65–5.5 V V_CC, but only rated to +85 °C (not 125 °C); 24 mA drive at 3.3 V; no AEC-Q100 qualification.	Not suitable for under-hood automotive or extended-temperature industrial use; acceptable for commercial-grade consumer electronics.	Select SN74LVC04APWR only if ambient temperature stays ≤85 °C and automotive qualification is unnecessary.
74AUP1G04GW,125	Single-gate variant (not hex); ultra-low ICC (0.9 µA typ); V_CC = 0.8–3.6 V only; no 5 V input tolerance.	Requires six separate packages for equivalent functionality; incompatible with 5 V signal sources; limited to sub-3.6 V systems.	Choose 74AUP1G04GW,125 only for ultra-low-power, single-channel needs in 1.8 V/2.5 V-only designs.

Compared with SN74LVC04APWR and 74AUP1G04GW,125, the MC74LCX04DTR2 uniquely combines AEC-Q100 qualification, 5 V input tolerance at full −40 °C to +125 °C range, and hex integration in TSSOP-14-making it the sole option for automotive body electronics requiring drop-in reliability and mixed-voltage interoperability.

Availability

MC74LCX04DTR2 is available at Aetrix Electronics and suitable for automotive body control modules, industrial PLC I/O interfaces, medical patient monitor data buses, and consumer IoT hub power sequencing requiring stable component supply and long-term lifecycle support.

Supply support for MC74LCX04DTR2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, logic, and sensor solutions for automotive, industrial, and cloud infrastructure markets.

The MC74LCX04DTR2 belongs to the LCX low-voltage CMOS logic family, designed specifically for mixed-voltage system interfacing with emphasis on 5 V-tolerant inputs, wide V_CC range, and automotive-grade reliability.

FAQ

What is the maximum input voltage the MC74LCX04DTR2 can tolerate when V_CC = 3.3 V?

The MC74LCX04DTR2 supports DC input voltages up to +6.5 V regardless of V_CC level, per its Absolute Maximum Ratings table. When V_CC = 3.3 V, this enables safe interfacing with standard 5 V TTL outputs without clamping diodes or external protection. This specification is verified across −40 °C to +125 °C and is intrinsic to the input structure of the MC74LCX04DTR2.

Does the MC74LCX04DTR2 require external pull-up or pull-down resistors on unused inputs?

Yes - the MC74LCX04DTR2 datasheet explicitly requires all unused inputs to be tied to either V_CC or GND. Floating CMOS inputs can cause increased ICC, oscillation, or excessive power dissipation due to indeterminate logic states. This requirement applies to every unused A0–A5 input on the MC74LCX04DTR2 and is not optional for stable operation.

Is the MC74LCX04DTR2 pin-compatible with the standard 74HC04 or 74LS04?

No - the MC74LCX04DTR2 uses the same 14-pin TSSOP layout as generic hex inverters, but its electrical behavior differs significantly: it has 5 V-tolerant inputs, wider V_CC range (1.65–5.5 V), and higher drive strength (±24 mA at 3.0 V). While pinout matches SOIC/TSSOP footprints, substituting MC74LCX04DTR2 for 74HC04/74LS04 requires verifying V_CC, loading, and timing margins in the target design.

What is the thermal resistance (θ_JA) of the MC74LCX04DTR2 in its TSSOP-14 package?

The MC74LCX04DTR2 in TSSOP-14 (Case 948G) has a junction-to-ambient thermal resistance (θ_JA) of 150 °C/W, measured per JESD51-7 on an FR4 board with 76 mm × 114 mm, 2-ounce copper. This value assumes still air and defines the maximum allowable power dissipation before junction temperature exceeds +150 °C - a key derating factor for the MC74LCX04DTR2 in high-density layouts.

Can the MC74LCX04DTR2 be used in a 1.8 V system with 5 V inputs present on other channels?

Yes - the MC74LCX04DTR2 is explicitly designed for this scenario. At V_CC = 1.8 V, its inputs remain tolerant to 5 V signals, enabling reliable level shifting. The VIH/VIL thresholds scale appropriately (e.g., VIH = 0.65 × V_CC ≈ 1.17 V), and propagation delay remains ≤10 ns (1.65–1.95 V range), making the MC74LCX04DTR2 suitable for 1.8 V core logic interfacing with 5 V peripherals.

MC74LCX04DTR2 Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: 74LCX

Package/Case:: 14-TSSOP (0.173", 4.40mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Logic Type:: Inverter

Number of Circuits:: 6

Number of Inputs:: 1

Features:: -

Voltage - Supply:: 2V ~ 3.6V

Current - Quiescent (Max):: 10 µA

Current - Output High, Low:: 24mA, 24mA

Input Logic Level - Low:: 0.7V ~ 0.8V

Input Logic Level - High:: 1.7V ~ 2V

Max Propagation Delay @ V, Max CL:: 5.2ns @ 3.3V, 50pF

Operating Temperature:: -55°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 14-TSSOP

MC74LCX04DTR2 FAQ

1.How can I place an order for MC74LCX04DTR2 through Aetrix?

Please submit a Request for Quotation (RFQ) for MC74LCX04DTR2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MC74LCX04DTR2 reliable?

The price and inventory of MC74LCX04DTR2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC74LCX04DTR2 is usually 5 days.

3.What payment methods are accepted for MC74LCX04DTR2?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC74LCX04DTR2 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MC74LCX04DTR2?

MC74LCX04DTR2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MC74LCX04DTR2 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MC74LCX04DTR2?

For technical support, including MC74LCX04DTR2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC74LCX04DTR2 requirements.

6.How does Aetrix verify that MC74LCX04DTR2 is sourced from the original manufacturer or authorized distributors?

All MC74LCX04DTR2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC74LCX04DTR2 meets industry standards.

7.What is the process for return or replacement of MC74LCX04DTR2?

All MC74LCX04DTR2 units undergo pre-shipment inspection (PSI). If there is an issue with MC74LCX04DTR2, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MC74LCX04DTR2 part is unused and in its original packaging.

Return procedure for MC74LCX04DTR2:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…