Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

onsemi MC74LVX125D

Name: MC74LVX125D
Brand: onsemi
SKU: MC74LVX125D
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: MC74LVX125D

Manufacturer:: onsemi

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 14-SOIC (0.154", 3.90mm Width)

Datasheet:: MC74LVX125D.pdf

Description:: IC BUF NON-INVERT 3.6V 14SOIC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,472

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

MC74LVX125D from onsemi is a quad 3-state bus buffer with 5 V-tolerant inputs, designed for level-shifting between 3.3 V logic domains and legacy 5 V systems. It features 4.4 ns typical propagation delay at 3.3 V, ±25 mA output drive, and operates across −40°C to +85°C. Used in bidirectional data bus isolation in industrial control backplanes and low-voltage microcontroller I/O expansion.

For engineers reviewing the MC74LVX125D datasheet, pinout, applications, or equivalent options, key selection criteria include 5 V input tolerance, 3-state timing (tPZL/tPLZ), SOIC-14 or TSSOP-14 package compatibility, and quiescent current ≤4 µA - all critical for mixed-voltage interface design and power-sensitive embedded systems.

Technical Context

The MC74LVX125D implements four independent non-inverting buffers, each with dedicated active-high 3-state enable (OE_n). Inputs tolerate up to 6.5 V DC, enabling direct connection to 5 V signals without external level shifters while powered from 2.0–3.6 V supplies.

Its CMOS architecture delivers balanced t_PLH/t_PHL propagation delays, low dynamic noise (V_OLP ≤ 0.5 V), and latchup immunity >300 mA. The device supports clean bus sharing via controlled output disable timing (t_PLZ = 8.3 ns max at 3.3 V) and tight output-to-output skew (≤1.5 ns).

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	2.0 V to 3.6 V - Enables operation in modern 3.3 V and battery-powered 2.5 V systems.
Input Voltage Tolerance	−0.5 V to +6.5 V - Allows direct interfacing with 5 V TTL/CMOS signals without external clamping.
t_PD (Typ)	4.4 ns at V_CC = 3.3 V, C_L = 15 pF - Supports >100 MHz bus toggle rates in high-speed digital interfaces.
I_OUT (per pin)	±25 mA - Sufficient to drive multiple standard CMOS loads or short PCB traces without buffering.
I_CC (Max)	4.0 µA at T_A = 25°C - Enables ultra-low static power in always-on monitoring circuits.
Operating Temp	−40°C to +85°C - Qualified for industrial temperature range deployment in factory automation and outdoor electronics.
ESD HBM	>2000 V - Provides robust handling margin during board assembly and field service.

Pinout & Package

MC74LVX125D is available in SOIC-14 NB (Case 751A) and TSSOP-14 (Case 948G) packages. Both are 14-pin surface-mount packages with 1.27 mm pitch (SOIC) or 0.65 mm pitch (TSSOP). Pin numbering follows standard dual-inline convention with Pin 1 marked by notch or dot.

Pin/Terminal	Circuit Role	Design Meaning
1, 4, 10, 13	OEn (Output Enable n)	Active-high enable for corresponding buffer (n = 0–3); drives output to high-impedance when low.
2, 5, 9, 12	Dn (Data Input n)	Non-inverting input for buffer n; accepts 0–6.5 V logic levels regardless of V_CC.
3, 6, 8, 11	On (Output n)	3-state buffered output; mirrors Dn when OEn = HIGH, high-Z when OEn = LOW.
7	GND	Ground reference for all logic and power domains; must be low-impedance for noise control.
14	V_CC	Positive supply (2.0–3.6 V); powers internal logic and output drivers; decoupling required near pin.

Key Features

Feature	Design Value
5 V-tolerant inputs	Supports seamless integration into mixed-voltage systems without external level translators.
4.4 ns propagation delay	Enables reliable timing closure in 3.3 V bus architectures operating up to 100 MHz.
Power-down input protection	Prevents damage or leakage when inputs are driven while V_CC is unpowered or ramping.
Low dynamic noise (V_OLP ≤ 0.5 V)	Reduces crosstalk and ground bounce in dense PCB layouts with shared power/ground planes.
Pb-free & RoHS compliant	Meets global environmental compliance requirements for industrial and consumer manufacturing.

Applications

Industrial PLC Backplane	Microcontroller I/O Expansion
Use Scenario: Isolating and level-shifting address/data lines between a 3.3 V ARM Cortex-M7 CPU and legacy 5 V peripheral modules on a modular control rack. IC Role / Device Role / Timing Role: Quad non-inverting buffer with per-channel 3-state control, enabling time-multiplexed bus arbitration and voltage domain bridging. Use Value: Eliminates need for discrete level shifters, reduces BOM count by 4×, and maintains signal integrity with <1.5 ns inter-output skew.	Use Scenario: Expanding GPIO count of an STM32L4 MCU by driving eight parallel sensors via two MC74LVX125D devices in 3-state mode. IC Role / Device Role / Timing Role: Bidirectional bus buffer enabling software-controlled directionality and hot-swap-safe I/O isolation. Use Value: Delivers 25 mA sink/source per line to directly drive LED indicators or optocoupler inputs without external drivers.
Automotive Body Control Module	Test Equipment Signal Conditioning
Use Scenario: Interfacing a 3.3 V CAN controller's diagnostic port with 5 V-compatible UART debug headers in a vehicle ECU. IC Role / Device Role / Timing Role: Unidirectional voltage translator with fail-safe high-impedance state during power sequencing. Use Value: Guarantees no signal contention during cold boot; withstands automotive load-dump transients due to 6.5 V input rating.	Use Scenario: Buffering and isolating logic-level trigger signals between FPGA-based pattern generators and DUTs with varying supply voltages. IC Role / Device Role / Timing Role: Low-skew, low-noise repeater ensuring deterministic timing alignment across multi-board test fixtures. Use Value: Maintains sub-nanosecond edge fidelity (t_PLH/t_PHL match ≤0.2 ns) critical for jitter-sensitive ATE applications.

Industrial PLC Backplane

Microcontroller I/O Expansion

Use Scenario: Isolating and level-shifting address/data lines between a 3.3 V ARM Cortex-M7 CPU and legacy 5 V peripheral modules on a modular control rack.

IC Role / Device Role / Timing Role: Quad non-inverting buffer with per-channel 3-state control, enabling time-multiplexed bus arbitration and voltage domain bridging.

Use Value: Eliminates need for discrete level shifters, reduces BOM count by 4×, and maintains signal integrity with <1.5 ns inter-output skew.

Use Scenario: Expanding GPIO count of an STM32L4 MCU by driving eight parallel sensors via two MC74LVX125D devices in 3-state mode.

IC Role / Device Role / Timing Role: Bidirectional bus buffer enabling software-controlled directionality and hot-swap-safe I/O isolation.

Use Value: Delivers 25 mA sink/source per line to directly drive LED indicators or optocoupler inputs without external drivers.

Automotive Body Control Module

Test Equipment Signal Conditioning

Use Scenario: Interfacing a 3.3 V CAN controller's diagnostic port with 5 V-compatible UART debug headers in a vehicle ECU.

IC Role / Device Role / Timing Role: Unidirectional voltage translator with fail-safe high-impedance state during power sequencing.

Use Value: Guarantees no signal contention during cold boot; withstands automotive load-dump transients due to 6.5 V input rating.

Use Scenario: Buffering and isolating logic-level trigger signals between FPGA-based pattern generators and DUTs with varying supply voltages.

IC Role / Device Role / Timing Role: Low-skew, low-noise repeater ensuring deterministic timing alignment across multi-board test fixtures.

Use Value: Maintains sub-nanosecond edge fidelity (t_PLH/t_PHL match ≤0.2 ns) critical for jitter-sensitive ATE applications.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad 3-state buffer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC125APWR	Lower V_CC min (1.65 V), tighter VOL (0.55 V @ 24 mA), but only 5.5 V input tolerant.	Better suited for ultra-low-voltage 1.8 V systems; insufficient for 6 V transient environments.	Select when operating below 2.0 V or requiring higher drive strength; avoid where 6.5 V input margin is mandatory.
74AHC125PW,118	Wider V_CC range (2.0–5.5 V), faster t_PD (2.5 ns), but no 5 V-tolerant inputs - inputs limited to V_CC.	Requires external clamping for 5 V signals; not drop-in compatible in mixed-voltage designs.	Choose for pure 3.3 V or 5 V systems needing maximum speed; reject if interfacing 5 V sources directly.

Compared with SN74LVC125APWR and 74AHC125PW,118, the MC74LVX125D uniquely combines 6.5 V input tolerance with sub-5 ns delay and µA-level quiescent current - making it the only option that safely bridges 5 V peripherals to 3.3 V controllers without redesigning signal conditioning.

Availability

MC74LVX125D is available at Aetrix Electronics and suitable for industrial PLC backplanes, microcontroller I/O expansion, automotive body control modules, and test equipment signal conditioning requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for MC74LVX125D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, logic, and sensor solutions for automotive, industrial, and cloud infrastructure markets.

The MC74LVX125D belongs to onsemi's LVX low-voltage logic family, engineered for interoperability between 3.3 V and 5 V systems while minimizing power consumption and electromagnetic interference in space-constrained embedded designs.

FAQ

What is the maximum input voltage the MC74LVX125D can safely accept?

The MC74LVX125D supports DC input voltages from −0.5 V to +6.5 V, independent of V_CC. This 6.5 V absolute maximum rating enables direct connection to 5 V logic families without external protection diodes or level shifters, and accommodates transient overvoltage events common in industrial environments. Always ensure input current remains within ±20 mA limits per pin.

Does the MC74LVX125D support true bidirectional data flow?

No, the MC74LVX125D is a unidirectional non-inverting buffer with separate input (Dn), output (On), and enable (OEn) terminals. It does not implement automatic direction sensing or bus transceiver functionality. For bidirectional operation, external control logic must manage OE states and signal routing - the MC74LVX125D itself only passes data from Dn to On when OEn is asserted.

What is the recommended decoupling strategy for the MC74LVX125D?

Place a 100 nF X7R ceramic capacitor between V_CC (Pin 14) and GND (Pin 7) as close as possible to the device - ideally within 3 mm trace length. For boards with multiple MC74LVX125D units or high-frequency switching, add a 4.7 µF bulk capacitor per power rail segment. Avoid shared vias between decoupling paths to maintain low-inductance return paths.

Can the MC74LVX125D be used with a 2.5 V supply voltage?

Yes, the MC74LVX125D is fully specified for V_CC = 2.0 V to 3.6 V, including 2.5 V operation. At 2.5 V, VOH is guaranteed ≥2.0 V (with IOH = −4 mA) and VOL ≤0.36 V (with IOL = 4 mA), meeting standard LVTTL thresholds. Propagation delay increases to ~6.2 ns (typ) at 2.5 V, which remains suitable for most 25–50 MHz bus applications.

Is the MC74LVX125D pin-compatible with older 74LS125 devices?

No, the MC74LVX125D is not pin-compatible with 74LS125. While both are quad 3-state buffers, the MC74LVX125D uses a different pin assignment: OE0/D0/O0/OE1/D1/O1/GND/VCC/OE2/D2/O2/OE3/D3/O3 (SOIC-14), whereas 74LS125 places GND at Pin 7 and VCC at Pin 14 but assigns OEs and outputs differently. Direct replacement requires PCB layout revision.

MC74LVX125D Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: 74LVX

Package/Case:: 14-SOIC (0.154", 3.90mm Width)

Packaging:: Tube

Product Status:: Obsolete

Logic Type:: Buffer, Non-Inverting

Number of Elements:: 4

Number of Bits per Element:: 1

Input Type:: -

Output Type:: 3-State

Current - Output High, Low:: 4mA, 4mA

Voltage - Supply:: 2V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 14-SOIC

MC74LVX125D FAQ

1.How can I place an order for MC74LVX125D through Aetrix?

Please submit a Request for Quotation (RFQ) for MC74LVX125D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MC74LVX125D reliable?

The price and inventory of MC74LVX125D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC74LVX125D is usually 5 days.

3.What payment methods are accepted for MC74LVX125D?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC74LVX125D transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MC74LVX125D?

MC74LVX125D orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MC74LVX125D order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MC74LVX125D?

For technical support, including MC74LVX125D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC74LVX125D requirements.

6.How does Aetrix verify that MC74LVX125D is sourced from the original manufacturer or authorized distributors?

All MC74LVX125D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC74LVX125D meets industry standards.

7.What is the process for return or replacement of MC74LVX125D?

All MC74LVX125D units undergo pre-shipment inspection (PSI). If there is an issue with MC74LVX125D, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MC74LVX125D part is unused and in its original packaging.

Return procedure for MC74LVX125D:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…