Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

onsemi MC74VHC1G09DFT2G-L22038

Name: MC74VHC1G09DFT2G-L22038
Brand: onsemi
SKU: MC74VHC1G09DFT2G-L22038
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: MC74VHC1G09DFT2G-L22038

Manufacturer:: onsemi

Category:: Gates and Inverters

Package:: 5-TSSOP, SC-70-5, SOT-353

Datasheet:: MC74VHC1G09DFT2G-L22038.pdf

Description:: IC GATE AND 1CH 2-INP SC88A

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:16,579

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

MC74VHC1G09DFT2G-L22038 from onsemi is a single 2-input AND gate with open-drain output, fabricated in advanced CMOS silicon-gate technology. It operates from 2.0 V to 5.5 V, delivers 4.3 ns propagation delay at 5 V (typ), supports 8 mA output drive at 3.0 V, and enables level-shifting between 3 V and 5 V systems in interface logic applications.

For engineers reviewing the MC74VHC1G09DFT2G-L22038 datasheet, pinout, applications, or equivalent options, key selection criteria include open-drain compatibility with wired-AND bus structures, overvoltage-tolerant inputs up to 5.5 V independent of VCC, IOFF partial power-down protection, and SC-88A package suitability for space-constrained PCB layouts.

Technical Context

The MC74VHC1G09DFT2G-L22038 implements standard positive-logic AND functionality with an open-drain output stage, requiring an external pull-up resistor for high-level assertion. Its input structure tolerates voltages up to 5.5 V regardless of VCC, enabling robust interfacing across mixed-supply domains.

IOFF circuitry actively disables input/output paths when VCC = 0 V, preventing back-powering and current leakage during partial power-down states. The device exhibits 6.2 ns tPZL and 6.5 ns tPLZ (typ) at 3.3 V with 15 pF load, confirming high-speed operation while maintaining CMOS power efficiency.

Key Specifications

Parameter	Value and Actual Design Meaning
VCC Range	2.0 V to 5.5 V - supports dual-supply system interfacing without level translators
tPD (5 V, CL=15 pF)	4.3 ns (typ) - enables timing-critical glue logic in sub-10 ns signal paths
IOL (3.0 V)	8 mA - sufficient to drive standard TTL loads or multiple CMOS inputs
VIN Tolerance	Up to 5.5 V - allows safe connection to 5 V buses while powered from 3 V
IOFF Leakage	1.0 μA max at 0 V VCC - prevents unintended current flow during power sequencing
Operating Temp	−55 °C to +125 °C - qualified for automotive under-hood and industrial control environments

Pinout & Package

MC74VHC1G09DFT2G-L22038 is packaged in SC-88A (SOT-353), a 5-pin, 1.25 mm × 2.1 mm surface-mount package with 0.65 mm pitch and moisture sensitivity level 1.

Pin/Terminal	Circuit Role	Design Meaning
1	Input B	Second logic input; accepts 0–5.5 V regardless of VCC
2	Input A	Primary logic input; compatible with 3.3 V and 5 V logic families
3	GND	Ground reference for supply and signal integrity
4	Output Y	Open-drain output; requires external pull-up for HIGH state
5	VCC	Positive supply rail; powers internal logic and enables IOFF protection

Key Features

Feature	Design Value
Overvoltage-tolerant inputs	Withstands 5.5 V input regardless of VCC - eliminates need for external clamping diodes in mixed-voltage interfaces
IOFF partial power-down	Blocks current path when VCC = 0 V - prevents backfeeding and ensures clean power sequencing in hot-swap systems
Open-drain output architecture	Enables wired-AND bus configurations and I²C-compatible signaling without additional components
Low dynamic power consumption	CPD = 8.0 pF - minimizes switching current in high-frequency enable/control paths

Applications

Industrial Sensor Interface	I²C Bus Level Translation
Use Scenario: Connecting 5 V analog sensor outputs to a 3.3 V microcontroller ADC input with digital enable control. IC Role / Device Role / Timing Role: AND gate enables/disables sensor data path synchronously with MCU readiness signal; open-drain output interfaces directly to 3.3 V I²C SDA line. Use Value: Eliminates discrete MOSFET level shifter; overvoltage tolerance protects MCU GPIO from 5 V transients during power-up sequencing.	Use Scenario: Bidirectional voltage translation between 5 V master and 3.3 V slave on shared I²C bus. IC Role / Device Role / Timing Role: Configured as open-drain buffer with pull-ups on both sides; performs logic AND of master/slave drive signals to enforce bus arbitration. Use Value: Enables interoperability without dedicated level translator ICs; IOFF prevents contention during slave power-down.
Hot-Swappable Module Control	Legacy System Glue Logic
Use Scenario: Enabling power delivery to a hot-pluggable peripheral only when both insertion detect and system ready signals are asserted. IC Role / Device Role / Timing Role: Dual-input AND gate with open-drain output drives enable pin of load switch; IOFF blocks leakage when module is unpowered. Use Value: Ensures zero current draw during insertion/removal; overvoltage-tolerant inputs accept 5 V detection signal while powered from 3.3 V rail.	Use Scenario: Adapting legacy 5 V TTL control signals to modern low-voltage FPGA configuration pins. IC Role / Device Role / Timing Role: Performs logic gating of reset and clock-enable signals before routing to 2.5 V/3.3 V FPGA; open-drain output accommodates FPGA's weak internal pull-ups. Use Value: Provides timing-compliant signal conditioning (4.3 ns tPD) without adding propagation delay skew across parallel control lines.

Industrial Sensor Interface

I²C Bus Level Translation

Use Scenario: Connecting 5 V analog sensor outputs to a 3.3 V microcontroller ADC input with digital enable control.

IC Role / Device Role / Timing Role: AND gate enables/disables sensor data path synchronously with MCU readiness signal; open-drain output interfaces directly to 3.3 V I²C SDA line.

Use Value: Eliminates discrete MOSFET level shifter; overvoltage tolerance protects MCU GPIO from 5 V transients during power-up sequencing.

Use Scenario: Bidirectional voltage translation between 5 V master and 3.3 V slave on shared I²C bus.

IC Role / Device Role / Timing Role: Configured as open-drain buffer with pull-ups on both sides; performs logic AND of master/slave drive signals to enforce bus arbitration.

Use Value: Enables interoperability without dedicated level translator ICs; IOFF prevents contention during slave power-down.

Hot-Swappable Module Control

Legacy System Glue Logic

Use Scenario: Enabling power delivery to a hot-pluggable peripheral only when both insertion detect and system ready signals are asserted.

IC Role / Device Role / Timing Role: Dual-input AND gate with open-drain output drives enable pin of load switch; IOFF blocks leakage when module is unpowered.

Use Value: Ensures zero current draw during insertion/removal; overvoltage-tolerant inputs accept 5 V detection signal while powered from 3.3 V rail.

Use Scenario: Adapting legacy 5 V TTL control signals to modern low-voltage FPGA configuration pins.

IC Role / Device Role / Timing Role: Performs logic gating of reset and clock-enable signals before routing to 2.5 V/3.3 V FPGA; open-drain output accommodates FPGA's weak internal pull-ups.

Use Value: Provides timing-compliant signal conditioning (4.3 ns tPD) without adding propagation delay skew across parallel control lines.

Equivalent & Alternatives

The following parts are listed as comparable options for similar AND gate with open-drain output applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC1G09DBVR	Same SC-70-5 package; 3.3 V optimized (1.65–5.5 V); slightly higher VOL (0.55 V @ 24 mA)	LVC family offers higher drive strength but tighter VCC dependency for overvoltage tolerance	Prefer when driving heavier capacitive loads or requiring tighter VOL spec at 3.3 V
74AUP1G09GW,125	Ultra-low power (0.9–3.6 V); 13 ns tPD at 3.3 V; smaller XSON-6 package (1.2 × 1.0 mm)	AUP family targets battery-powered systems where quiescent current (< 0.5 μA) dominates timing requirements	Choose when minimizing standby power is critical and 13 ns delay is acceptable

Compared with SN74LVC1G09DBVR and 74AUP1G09GW,125, the MC74VHC1G09DFT2G-L22038 provides superior overvoltage tolerance (5.5 V independent of VCC), faster propagation (4.3 ns vs. ≥6.2 ns), and proven IOFF behavior-making it optimal for mixed-supply industrial control and hot-swap interfaces where robustness outweighs ultra-low power needs.

Availability

MC74VHC1G09DFT2G-L22038 is available at Aetrix Electronics and suitable for industrial sensor interfaces, I²C bus translation, hot-swappable module control, and legacy system glue logic requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for MC74VHC1G09DFT2G-L22038 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.

The MC74VHC1G09DFT2G-L22038 belongs to the VHC (Very High Speed CMOS) logic family, designed specifically for high-speed, low-power interface and level-shifting applications in mixed-voltage embedded systems.

FAQ

What is the maximum input voltage rating for MC74VHC1G09DFT2G-L22038, and does it depend on VCC?

The MC74VHC1G09DFT2G-L22038 supports DC input voltages up to 5.5 V regardless of VCC value - meaning it safely accepts 5 V signals even when powered from 2.0 V or 3.3 V. This overvoltage tolerance is built into the input structure and does not require external clamping components, making MC74VHC1G09DFT2G-L22038 ideal for bridging legacy and modern logic domains without level shifters.

Does MC74VHC1G09DFT2G-L22038 support partial power-down operation, and how is it implemented?

Yes, MC74VHC1G09DFT2G-L22038 features IOFF circuitry that automatically disables input and output paths when VCC = 0 V. This prevents back-current flow through I/O pins during power sequencing or hot-swap events. Measured IOFF leakage is ≤10 μA across −55 °C to +125 °C, ensuring reliable isolation in systems where subsystems power up/down independently - a key requirement for MC74VHC1G09DFT2G-L22038 in modular industrial controllers.

What is the typical propagation delay of MC74VHC1G09DFT2G-L22038 at 3.3 V and 5 V supply voltages?

At VCC = 5.0 V with CL = 15 pF, MC74VHC1G09DFT2G-L22038 achieves 4.3 ns (typ) tPZL and 4.8 ns (typ) tPLZ. At VCC = 3.3 V under identical conditions, delay increases to 6.2 ns (typ) tPZL and 6.5 ns (typ) tPLZ. These values are guaranteed across −40 °C to +85 °C operating range, confirming MC74VHC1G09DFT2G-L22038's suitability for timing-critical enable and handshake logic in real-time embedded systems.

Can MC74VHC1G09DFT2G-L22038 be used as a level translator between 5 V and 3.3 V I²C buses?

Yes, MC74VHC1G09DFT2G-L22038 can implement bidirectional I²C level translation using its open-drain output and overvoltage-tolerant inputs. With separate pull-ups on each side of the bus and proper signal routing (e.g., A = master SDA, B = slave SDA, Y = shared SDA), MC74VHC1G09DFT2G-L22038 enforces wired-AND arbitration while blocking reverse current. Its IOFF function further isolates the bus during slave power-down - a capability verified in onsemi application notes for MC74VHC1G09DFT2G-L22038.

What package type is used for MC74VHC1G09DFT2G-L22038, and what are its key mechanical dimensions?

MC74VHC1G09DFT2G-L22038 uses the SC-88A (also known as SOT-353 or SC-70-5) package: 5-pin, 1.25 mm × 2.1 mm body size, 0.65 mm lead pitch, and 0.95 mm maximum height. It complies with JEDEC MO-203-AB and is rated MSL Level 1 - meaning unlimited floor life at ≤30 °C/60% RH. This compact, RoHS-compliant package supports high-density PCB layouts required for MC74VHC1G09DFT2G-L22038 in portable and space-constrained industrial modules.

MC74VHC1G09DFT2G-L22038 Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: 74VHC

Package/Case:: 5-TSSOP, SC-70-5, SOT-353

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Logic Type:: AND Gate

Number of Circuits:: 1

Number of Inputs:: 2

Features:: Open Drain

Voltage - Supply:: 2V ~ 5.5V

Current - Quiescent (Max):: 1 µA

Current - Output High, Low:: -, 8mA

Input Logic Level - Low:: 0.5V ~ 1.65V

Input Logic Level - High:: 1.5V ~ 3.85V

Max Propagation Delay @ V, Max CL:: 7.9ns @ 5V, 50pF

Operating Temperature:: -55°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: SC-88A (SC-70-5/SOT-353)

MC74VHC1G09DFT2G-L22038 FAQ

1.How can I place an order for MC74VHC1G09DFT2G-L22038 through Aetrix?

Please submit a Request for Quotation (RFQ) for MC74VHC1G09DFT2G-L22038 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MC74VHC1G09DFT2G-L22038 reliable?

The price and inventory of MC74VHC1G09DFT2G-L22038 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC74VHC1G09DFT2G-L22038 is usually 5 days.

3.What payment methods are accepted for MC74VHC1G09DFT2G-L22038?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC74VHC1G09DFT2G-L22038 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MC74VHC1G09DFT2G-L22038?

MC74VHC1G09DFT2G-L22038 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MC74VHC1G09DFT2G-L22038 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MC74VHC1G09DFT2G-L22038?

For technical support, including MC74VHC1G09DFT2G-L22038 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC74VHC1G09DFT2G-L22038 requirements.

6.How does Aetrix verify that MC74VHC1G09DFT2G-L22038 is sourced from the original manufacturer or authorized distributors?

All MC74VHC1G09DFT2G-L22038 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC74VHC1G09DFT2G-L22038 meets industry standards.

7.What is the process for return or replacement of MC74VHC1G09DFT2G-L22038?

All MC74VHC1G09DFT2G-L22038 units undergo pre-shipment inspection (PSI). If there is an issue with MC74VHC1G09DFT2G-L22038, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MC74VHC1G09DFT2G-L22038 part is unused and in its original packaging.

Return procedure for MC74VHC1G09DFT2G-L22038:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…