NXP Semiconductors MC88920DW

Overview

MC88920DW from Freescale Semiconductor (formerly Motorola) is a low-skew CMOS PLL clock driver designed for CISC and single-processor RISC systems, specifically targeting MC68030/040 microprocessor clock distribution. It delivers six phase-locked outputs-including Q0–Q2 (≤500ps skew), Q3 (180° inverted), 2X_Q (50MHz max), and Q/2-with ±36mA CMOS/TTL-compatible drive strength and integrated reset-lock functionality.

For engineers reviewing the MC88920DW datasheet, MC88920DW pinout, MC88920DW application, or MC88920DW equivalent, key selection criteria include 2X_Q output compliance with 20/25MHz 68040 PCLK specs, guaranteed 3-cycle recovery after MR assertion, RST_OUT(LOCK) open-drain reset signaling with 1024-Q-cycle timing, and SOIC-20 package compatibility with analog/digital power isolation requirements.

Technical Context

The MC88920DW implements a charge-pump PLL with internal Q/2 feedback to enforce fixed 2× multiplication from SYNC input to 2X_Q output-no external feedback path required. Its VCO operates up to 50MHz, and all outputs (Q0–Q2, Q3, 2X_Q, Q/2) are phase- and frequency-locked to SYNC with part-to-part SYNC-to-Q skew <600ps.

It integrates dual-domain reset control: RST_IN/RST_OUT(LOCK) provides processor reset synchronization and lock indication for 68030/040 families, while MR independently resets only 2X_Q, Q0, and Q1-leaving Q2, Q3, and Q/2 active during partial power-down. PLL_EN enables static test mode by disabling the VCO without frequency limitation on SYNC input.

Key Specifications

Pinout & Package

DW suffix denotes 20-lead plastic SOIC package (Case 751D–04), 7.5 mm × 12.8 mm body, 1.27 mm pitch, with separate analog/digital ground and power pins (GND, GND(AN), VCC, VCC(AN)) for jitter-sensitive PLL operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PLL clock driver applications.

Compared with ICS8302AMLF and MC100EP131FN, the MC88920DW uniquely combines 5V-tolerant CMOS outputs, integrated 68030/040 reset coordination, fixed 2× PLL architecture, and SOIC-20 packaging-making it irreplaceable in legacy Motorola 68K system upgrades where electrical, timing, and software boot compatibility are mandatory.

Availability

MC88920DW is available at Aetrix Electronics and suitable for industrial control panels, legacy workstation repairs, telecom line card refurbishment, and embedded 68K-system design requiring stable component supply across extended product lifecycles.

Supply support for MC88920DW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Freescale Semiconductor (now part of NXP Semiconductors) was a leading designer of high-performance analog and mixed-signal ICs for computing, automotive, and industrial applications.

The MC88920DW belongs to Freescale's Timing Solutions portfolio, engineered specifically to simplify clock distribution and reset sequencing in Motorola 68000-family microprocessor systems.

FAQ

What is the maximum allowable SYNC input frequency for the MC88920DW?

The MC88920DW specifies a SYNC input frequency range of 5 MHz to 12.5 MHz, derived from the requirement that SYNC must be ≤ Fmax(2X_Q)/4 = 50 MHz / 4. This ensures stable 2× multiplication and meets the 20/25MHz 68040 PCLK timing envelope. Operation outside this range may prevent phase lock or violate AC timing specs such as tRISE/FALL and tCYCLE.

Does the MC88920DW require an external loop filter?

Yes-the MC88920DW requires an external loop filter consisting of a 1MΩ resistor connected to RC1 and a 0.1µF capacitor between RC1 and analog ground (or analog VCC), plus 330Ω and 47Ω resistors as shown in Figure 7 of the datasheet. This network stabilizes the charge pump and suppresses jitter; omitting it risks excessive phase noise and failure to achieve lock.

How does the RST_OUT(LOCK) pin behave during power-up of the MC88920DW?

When RST_IN is held high during power-up, RST_OUT(LOCK) remains actively low until the PLL achieves steady-state phase/frequency lock to SYNC. After lock, it transitions to high-impedance after 1024 Q-output cycles, allowing an external pull-up resistor to assert high. If RST_IN is held low, RST_OUT(LOCK) stays low indefinitely-enabling manual reset override independent of PLL status.

Can the MC88920DW operate with a 3.3V supply?

No-the MC88920DW is specified only for 5.0 V ±10% operation (4.5V to 5.5V). Its ±36mA output drive, input thresholds (VIH = 2.0V min), and internal PLL circuitry are designed for 5V TTL/CMOS compatibility. Applying 3.3V will result in undefined logic states, insufficient drive strength, and failure to meet AC timing or lock acquisition specs.

What is the purpose of the separate VCC(AN) and GND(AN) pins on the MC88920DW?

VCC(AN) and GND(AN) supply dedicated power and ground to the analog PLL core-including the VCO, phase-frequency detector, and charge pump-to isolate sensitive analog circuitry from digital switching noise. Routing these pins separately with local 0.1µF bypassing minimizes jitter and ensures reliable lock acquisition; sharing them with digital VCC/GND violates the recommended layout and degrades tSKEW and tLOCK performance.