NXP Semiconductors MC9328MX1DVH20

Overview

MC9328MX1DVH20 from NXP Semiconductors (formerly Freescale) is an ARM920T™-based applications processor operating at 200 MHz, featuring integrated SDRAM controller, LCD controller, USB device interface, MMC/SD host controller, and multimedia accelerators. It targets portable information appliances requiring rich UI, low-power operation, and peripheral integration.

For engineers reviewing the MC9328MX1DVH20 datasheet, MC9328MX1DVH20 pinout, MC9328MX1DVH20 application, or MC9328MX1DVH20 equivalent, key selection considerations include 256-pin MAPBGA-225 package compatibility, 1.7–1.9 V core voltage, 200 MHz clock speed, integrated LCD timing control, and USB 1.1 device functionality in industrial handheld and legacy Palm OS platforms.

Technical Context

The MC9328MX1DVH20 implements a 32-bit ARM920T™ core with Harvard architecture, 16 KB instruction and 16 KB data caches, and MMU support. Its system-on-chip architecture integrates dedicated modules including a 16-channel DMA controller, three UARTs with IrDA/auto-bauding, two SPI interfaces, dual SSI/I²S audio ports, and a real-time clock with sampling timer.

Power management includes dynamic PLL clock generation, multiple sleep modes, and independent voltage domains for core (QVDD), I/O (NVDD), and analog (AVDD) sections. The processor supports external memory via 24-bit address/32-bit data EIM bus and SDRAM controller with bank addressing, CAS/RAS control, and DQM masking.

Key Specifications

Pinout & Package

MC9328MX1DVH20 is housed in a 256-ball Mold Array Process Ball Grid Array (MAPBGA), Case 1304B-01, with 15 mm × 15 mm body size and 1.0 mm ball pitch. The package supports fine-pitch PCB routing and thermal dissipation via internal thermal pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar applications processor applications.

Compared with i.MX21 and PXA270, the MC9328MX1DVH20 delivers optimized power efficiency and integrated LCD timing for legacy Palm OS handhelds, while offering lower gate count and simpler power sequencing than its successors-making it ideal for cost-sensitive, long-lifecycle industrial PDAs where software stability outweighs raw compute density.

Availability

MC9328MX1DVH20 is available at Aetrix Electronics and suitable for industrial handheld terminals, legacy Palm OS devices, and medical data loggers requiring stable component supply and long-term obsolescence management.

Supply support for MC9328MX1DVH20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with roots in Philips and Freescale.

The i.MX family-including MC9328MX1DVH20-was designed specifically for portable, battery-powered information appliances demanding high integration, low active power, and rich multimedia peripheral support.

FAQ

What is the maximum supported SDRAM capacity for the MC9328MX1DVH20?

The MC9328MX1DVH20 supports up to 256 MB of SDRAM via its 11-bit row address (MA[10:0]), 4-bit bank address (SDBA[4:0]), and 10-bit column address (MA[9:0])-configured through the SDRAM Controller registers. This allows addressing four banks of 64 MB each. The MC9328MX1DVH20 datasheet specifies timing parameters for 16 Mbit × 16-bit and 32 Mbit × 16-bit SDRAM parts, confirming full compatibility with standard mobile SDRAM modules used in Palm OS devices.

Does the MC9328MX1DVH20 support USB host functionality?

No, the MC9328MX1DVH20 only implements a USB 1.1 device controller (not OTG or host). Its USBD_VP/VM and USBD_VPO/VMO pins are strictly for full-speed (12 Mbps) device-mode communication. External USB host capability requires a companion PHY or discrete hub IC. The MC9328MX1DVH20 does not contain USB host registers, descriptor handling logic, or root hub enumeration firmware-only device endpoint buffers and control state machines.

How is the LCD interface configured for non-Sharp panels?

The MC9328MX1DVH20 LCD controller supports generic TFT and STN panels via programmable timing registers (LCDC_LCSR, LCDC_LCCR), but Sharp HR-TFT-specific signals (SPL_SPR, PS, CLS, REV) are fixed-function outputs. For non-Sharp panels, those pins must be left unconnected or repurposed as GPIO. Standard 16-bit RGB output (LD[15:0]) and sync signals (FLM/VSYNC, LP/HSYNC, LSCLK) remain fully configurable for custom timing, with pixel clock derived from internal PLL dividers.

What is the function of the BOOT[3:0] pins on the MC9328MX1DVH20?

The BOOT[3:0] pins on the MC9328MX1DVH20 determine the boot source and configuration mode at power-on reset. Their strapped logic levels select between NOR flash, NAND flash, or serial ROM boot, and define bus width (8/16-bit), endian mode, and initial clock configuration. These pins are sampled once during reset assertion and cannot be reconfigured dynamically-the MC9328MX1DVH20 relies on this hardwired setup for reliable cold-start operation in field-deployed devices.

Can the MC9328MX1DVH20 operate with a 3.3 V I/O supply while maintaining 1.8 V core voltage?

Yes, the MC9328MX1DVH20 supports independent I/O and core supplies: NVDD (I/O) accepts 1.7–3.3 V, while QVDD (core) requires 1.7–1.9 V. This allows direct interfacing with 3.3 V peripherals (e.g., SD cards, UART transceivers) without level shifters. However, AVDD (analog) must be ≥ QVDD to prevent ESD diode forward-biasing, and all supply rails must meet sequencing requirements specified in the MC9328MX1DVH20 power-up timing diagram.