NXP Semiconductors MC9S08DN60ACLC
- Part No.:
- MC9S08DN60ACLC
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 32-LQFP
- Datasheet:
-
MC9S08DN60ACLC.pdf
- Description:
- IC MCU 8BIT 60KB FLASH 32LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,741
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MC9S08DN60ACLC from NXP (formerly Freescale) is an 8-bit HCS08 microcontroller with 60 KB flash, 2 KB RAM, and 2 KB EEPROM, featuring a 40-MHz CPU core (20-MHz bus), 12-bit ADC with temperature sensor, dual analog comparators, LIN-capable SCI, SPI, I²C, two TPM modules (6+2 channels), RTC, and real-time interrupt capability. It targets automotive body electronics and industrial control systems requiring robust on-chip peripherals and low-power operation.
For engineers reviewing the MC9S08DN60ACLC datasheet, MC9S08DN60ACLC pinout, MC9S08DN60ACLC application, or MC9S08DN60ACLC equivalent, key selection considerations include its 64-pin LQFP package, 53 GPIOs with configurable slew rate and pull devices, integrated MCG clock generator with FLL/PLL modes, and support for Stop2/Stop3 low-power modes with RTC wake-up.
Technical Context
The MC9S08DN60ACLC implements the S08CPUV3 core with HC08 instruction set plus BGND, supporting up to 32 interrupt/reset sources and single-wire background debug. Its Multi-Purpose Clock Generator (MCG) provides FLL (±1.5% accuracy with internal temp-compensated reference) and PLL modes, factory-trimmed internal reference, and external crystal/resonator support (31.25 kHz–16 MHz).
Peripherals include a 16-channel 12-bit ADC with 2.5 μs conversion time and automatic compare, two analog comparators with bandgap reference option, SCI1 compliant with LIN 2.0 and SAE J2602, and dual TPM modules supporting input capture, output compare, and edge-aligned PWM - all operable in Wait and Stop modes with RTC-driven wake-up.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | HCS08 (S08CPUV3), 40-MHz max core frequency, 20-MHz bus speed - enables deterministic real-time execution at high throughput. |
| Flash Memory | 60 KB on-chip flash with read/program/erase over full voltage/temperature range - supports field firmware updates and secure code storage. |
| RAM / EEPROM | 2 KB SRAM for runtime variables; 2 KB EEPROM with 4-/8-byte erase sectors - retains critical calibration or configuration data across power cycles. |
| ADC | 16-channel, 12-bit resolution, 2.5 μs conversion time, internal bandgap and temperature sensor - enables precise analog monitoring without external components. |
| Low-Power Modes | Stop2 and Stop3 modes with RTC wake-up from 1-kHz internal oscillator - achieves sub-μA current draw while maintaining timekeeping and scheduled wake events. |
| Communication | SCI1 (LIN 2.0/J2602), SPI (master/slave, double-buffered), I²C (100 kbps, multi-master) - supports mixed-protocol vehicle networks and sensor interfacing. |
| Timers | TPM1 (6-channel) and TPM2 (2-channel) with input capture, output compare, PWM - provides flexible timing, motor control, and signal generation in compact footprint. |
Pinout & Package
MC9S08DN60ACLC is housed in a 64-pin LQFP (10×10 mm) package with 53 general-purpose I/O pins and one dedicated input-only pin. All I/Os support configurable pull devices, hysteresis, slew rate, and drive strength; 24 pins support edge-selectable interrupts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Power supply and ground | Dual power domains: VDD (core/analog I/O), VSS (digital/analog ground) - require separate decoupling for noise-sensitive ADC and digital logic. |
| XTAL, EXTAL | Crystal oscillator inputs | Supports 31.25 kHz–16 MHz crystals/resonators for precision clock source - used by MCG for FLL/PLL reference or RTC timing. |
| RESET | Active-low reset input | Asynchronous reset with internal pull-up; accepts external reset signals or power-on reset assertion - ensures reliable initialization under brownout or startup conditions. |
| BKGD/MS | Background debug / mode select | Single-wire debug interface pin - enables in-circuit programming and real-time emulation without dedicated JTAG pins. |
| VREFH, VREFL | ADC reference voltage terminals | Define 0 V to VREFH range for 12-bit conversions - allow ratiometric or absolute measurement depending on external reference connection. |
| AD0–AD15 | Analog input channels | 16 multiplexed ADC inputs shared with GPIO - enable simultaneous sensor monitoring (e.g., temperature, voltage, current) with minimal external circuitry. |
Key Features
| Feature | Design Value |
|---|---|
| On-chip MCG with FLL + PLL | Factory-trimmed internal reference (±1.5% FLL accuracy), external crystal support, and dynamic mode switching - eliminates need for external clock IC while enabling flexible clock tree design. |
| Real-time interrupt with RTC | Free-running 1-kHz internal oscillator powers RTC in Stop2/Stop3 modes - allows periodic wake-up for polling or scheduling without external components or power drain. |
| Flash security and block protection | Programmable flash block lock and illegal opcode/address detection - prevents unauthorized code access or execution, meeting basic automotive security requirements. |
| Single-wire BDM interface | Background debug via BKGD/MS pin only - reduces PCB routing complexity and debug connector footprint versus multi-pin JTAG solutions. |
| Configurable I/O electrical characteristics | Per-pin slew rate, drive strength, and pull-up/pull-down control - optimizes EMI, signal integrity, and power consumption across diverse peripheral interfaces. |
Applications
| Automotive Body Control Module (BCM) | Industrial Motor Drive Interface |
|---|---|
Use Scenario: Centralized control of door locks, window lifts, lighting, and mirror adjustment in 12 V vehicle platforms. IC Role / Device Role / Timing Role: Main system controller executing LIN slave protocol over SCI1, managing PWM-driven motor drivers via TPM outputs, and monitoring switch inputs and sensor feedback via ADC and ACMP. Use Value: Integrated LIN transceiver support, 53 GPIOs for discrete I/O expansion, and Stop-mode RTC wake-up reduce BOM count and enable ultra-low-power sleep states between user interactions. | Use Scenario: Closed-loop speed/torque control of BLDC or stepper motors in HVAC actuators and valve positioners. IC Role / Device Role / Timing Role: Real-time PWM generation (TPM1/TPM2), current/voltage sensing (12-bit ADC with 2.5 μs conversion), and fault detection (analog comparators with bandgap reference). Use Value: Sub-microsecond ADC timing and hardware-triggered conversions synchronize sampling with PWM edges, improving current loop stability without CPU overhead. |
| Smart Sensor Node with Local Decision Logic | Energy-Efficient Industrial Timer/Sequencer |
Use Scenario: Self-contained environmental monitor (temperature, humidity, voltage) with local alarm triggering and data logging to EEPROM. IC Role / Device Role / Timing Role: Sensor aggregator using ADC and ACMP inputs, local decision engine running on HCS08 core, non-volatile storage manager for calibration and event logs. Use Value: On-chip 2 KB EEPROM retains sensor offsets and thresholds across power loss; internal temperature sensor eliminates external thermal IC for basic compensation. | Use Scenario: Programmable delay timer, cyclic machine sequencer, or maintenance scheduler in factory equipment with battery backup. IC Role / Device Role / Timing Role: Precision timebase provider using RTC with external 32.768 kHz crystal, executing timed I/O actions via TPM outputs and waking from Stop3 mode on schedule. Use Value: RTC operates independently in Stop3 mode with <1 μA current draw - extends battery life for years in maintenance-free deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| S9S08DN60F1MLC | Same core, pin-compatible 64-pin LQFP; updated mask set (post-Rev 3), enhanced ESD rating (±8 kV HBM), and extended temperature range (−40°C to 105°C vs. −40°C to 85°C). | Preferred for new designs targeting extended ambient temperatures or higher ESD immunity in automotive cabin modules. | Select S9S08DN60F1MLC when operating above 85°C or requiring improved robustness in noisy environments; software compatible but verify flash security register behavior per Rev 4 errata. |
| MC9S08DZ60CLC | Same 60 KB flash, 2 KB RAM, and peripheral set; differs in oscillator range (supports 32 kHz–20 MHz), adds CAN 2.0B module, and uses 64-pin QFP (not LQFP) with different thermal pad layout. | Required where CAN bus integration is mandatory (e.g., gateway nodes), but introduces PCB redesign due to package and pinout differences. | Choose MC9S08DZ60CLC only if CAN communication is essential; not drop-in replaceable due to CAN pins replacing GPIOs and altered thermal pad geometry. |
Compared with MC9S08DN60ACLC, S9S08DN60F1MLC offers extended temperature and ESD specs with identical software and pinout, while MC9S08DZ60CLC adds CAN at the cost of package incompatibility and GPIO reduction - making the former a direct upgrade and the latter a functionally expanded but hardware-incompatible alternative.
Availability
MC9S08DN60ACLC is available at Aetrix Electronics and suitable for automotive body electronics, industrial motor interface modules, smart sensor nodes, and energy-efficient industrial timers requiring stable component supply and long-term lifecycle support.
Supply support for MC9S08DN60ACLC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with roots in Freescale's MCU heritage.
The MC9S08DN60ACLC belongs to the HCS08 family - designed for cost-sensitive, low-power embedded control in automotive body electronics and industrial systems where reliability, peripheral integration, and debug simplicity are critical.
FAQ
What is the maximum operating frequency of the MC9S08DN60ACLC CPU core?
The MC9S08DN60ACLC features an HCS08 CPU core with a maximum core frequency of 40 MHz, delivering a 20-MHz bus speed. This performance level supports real-time control tasks in automotive and industrial applications while maintaining low power consumption through intelligent clock gating and multiple low-power modes. The MC9S08DN60ACLC achieves this speed using its integrated Multi-Purpose Clock Generator with FLL or PLL configuration.
Does the MC9S08DN60ACLC support LIN communication natively?
Yes, the MC9S08DN60ACLC includes SCI1 hardware that fully supports LIN 2.0 and SAE J2602 protocols, including master extended break generation and slave extended break detection. This enables direct implementation of LIN slave nodes in automotive body control applications without external transceivers or protocol translation layers. The MC9S08DN60ACLC's SCI module handles framing, checksum, and synchronization in hardware, reducing CPU load during network communication.
How much EEPROM memory does the MC9S08DN60ACLC provide, and what are its key endurance characteristics?
The MC9S08DN60ACLC integrates 2 KB of on-chip EEPROM with 4-byte dual-page or 8-byte single-page erase sectors, supporting program and erase operations while executing Flash code. It guarantees 100,000 erase/write cycles and data retention exceeding 10 years at 85°C. This capability allows the MC9S08DN60ACLC to store calibration data, device configuration, or event logs reliably across power cycles without external non-volatile memory.
What low-power modes are available on the MC9S08DN60ACLC, and which peripherals remain active in Stop mode?
The MC9S08DN60ACLC supports two very low-power Stop modes (Stop2 and Stop3), a reduced-power Wait mode, and a real-time interrupt capable of waking from all three. In Stop2/Stop3, the RTC remains active using its 1-kHz internal oscillator, and selected TPM channels can be configured for wake-up on match. The MC9S08DN60ACLC maintains RAM contents and retains peripheral register settings, enabling fast resumption of operation after wake-up without full reinitialization.
Is the MC9S08DN60ACLC pin-compatible with other members of the DN-series, such as the MC9S08DN48ACLC?
No, the MC9S08DN60ACLC is not pin-compatible with lower-density variants like MC9S08DN48ACLC when packaged in the same 64-pin LQFP form factor - although they share identical pinouts, the MC9S08DN60ACLC requires full validation of flash security register usage and EEPROM sector mapping due to differences in memory partitioning. Always consult the specific device's mechanical drawing and register summary, as MC9S08DN60ACLC mask revisions may introduce subtle I/O behavior changes not present in earlier DN-series silicon.
MC9S08DN60ACLC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 32-LQFP
- Series:
- S08
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- S08
- Core Size:
- 8-Bit
- Speed:
- 40MHz
- Connectivity:
- I2C, LINbus, SCI, SPI
- Peripherals:
- LVD, POR, PWM, WDT
- Number of I/O:
- 25
- Program Memory Size:
- 60KB (60K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 2K x 8
- RAM Size:
- 2K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 10x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MC9S08DN60ACLC FAQ
1.How can I place an order for MC9S08DN60ACLC through Aetrix?
Please submit a Request for Quotation (RFQ) for MC9S08DN60ACLC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MC9S08DN60ACLC reliable?
The price and inventory of MC9S08DN60ACLC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC9S08DN60ACLC is usually 5 days.
3.What payment methods are accepted for MC9S08DN60ACLC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC9S08DN60ACLC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MC9S08DN60ACLC?
MC9S08DN60ACLC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MC9S08DN60ACLC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MC9S08DN60ACLC?
For technical support, including MC9S08DN60ACLC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC9S08DN60ACLC requirements.
6.How does Aetrix verify that MC9S08DN60ACLC is sourced from the original manufacturer or authorized distributors?
All MC9S08DN60ACLC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC9S08DN60ACLC meets industry standards.
7.What is the process for return or replacement of MC9S08DN60ACLC?
All MC9S08DN60ACLC units undergo pre-shipment inspection (PSI). If there is an issue with MC9S08DN60ACLC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MC9S08DN60ACLC part is unused and in its original packaging.
Return procedure for MC9S08DN60ACLC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MC9S08DN60ACLC Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

