NXP Semiconductors MCIMX357DJQ5C
- Part No.:
- MCIMX357DJQ5C
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 400-LFBGA
- Datasheet:
-
MCIMX357DJQ5C.pdf
- Description:
- IC MPU I.MX35 532MHZ 400LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:450
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Product details
Overview
MCIMX357DJQ5C from NXP Semiconductors (formerly Freescale) is an ARM1136JF-S-based multimedia applications processor operating at 532 MHz, integrating LCD controller, Ethernet MAC 10/100 Mbps, OpenVG 1.1 GPU, image processing unit (IPU), and dual CAN interfaces. It targets industrial HMI and display controllers requiring rich graphics, camera interface support (up to 30 Mpixels/s), and robust connectivity.
For engineers reviewing the MCIMX357DJQ5C datasheet, MCIMX357DJQ5C pinout, MCIMX357DJQ5C application, or MCIMX357DJQ5C equivalent, key selection criteria include its -20°C to +70°C industrial temperature grade, MAPBGA-5284 (17 × 17 mm, 0.8 mm pitch) package, 128-Kbyte L2 cache, integrated VFP11 coprocessor, and dual SDIO/MMC host support with CE-ATA capability.
Technical Context
The MCIMX357DJQ5C implements a hierarchical memory architecture with 16-Kbyte L1 instruction and data caches plus a unified 128-Kbyte L2 cache, reducing external bus bandwidth demand. Its ARM1136JF-S core (r1p3) supports Thumb®, Jazelle® Java acceleration, and SIMD DSP instructions for multimedia workloads.
It integrates domain-specific subsystems: Application Processor (AP) domain hosts the ARM11 core, GPU, IPU, and LCD controller; Shared domain includes Smart DMA (SDMA), External Memory Interface (EMI), and connectivity peripherals like FEC, USB OTG/Host, and dual FlexCAN. Power management uses clock gating, power gating, and well biasing to reduce leakage in 90-nm process.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | ARM1136JF-S (ARM v6), r1p3 revision - enables Thumb/Jazelle/DSP execution and MMU support for OS-level multitasking. |
| Clock Frequency | 532 MHz - delivers sustained performance for real-time video decode, UI rendering, and industrial control loops. |
| L2 Cache | 128 Kbytes unified - reduces latency to external DDR2/mobile DDR memory and improves throughput for graphics and imaging pipelines. |
| GPU | OpenVG 1.1-compliant 2D accelerator - offloads vector graphics rendering from CPU, enabling smooth SVG-based HMIs without software rasterization. |
| Memory Interfaces | DDR2/SDR/mobile DDR (up to 133 MHz), SLC/MLC NAND, NOR Flash, SRAM - supports flexible boot media and high-bandwidth frame buffers. |
| Connectivity | Dual CAN 2.0B, triple UART (4.0 Mbps), dual SDIO/MMC + CE-ATA, USB 2.0 OTG + Host (480 Mbps), 10/100 Mbps Ethernet - meets industrial fieldbus, storage, and wired network requirements. |
| Imaging | Parallel camera interface (4/8/10/16-bit, YUV/YCC, 30 Mpixels/s) + IPUv1 - enables real-time sensor preprocessing, rotation, blending, and display composition. |
Pinout & Package
MCIMX357DJQ5C is housed in a RoHS-compliant, lead-free MAPBGA package (Case 5284), 17 mm × 17 mm body, 0.8 mm ball pitch, MSL Level 3. Ball map corresponds to silicon revision 2.1 (Table 95/97).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EXT_ARMCLK | External ARM Clock Input | Allows synchronous clock sourcing from external oscillator for deterministic timing in safety-critical systems. |
| FEC_TXD[3:0] | Ethernet MAC Transmit Data | 4-bit parallel interface to external PHY; supports IEEE 802.3 10/100 Mbps baseband signaling. |
| USBOTG_DP/DM | USB 2.0 OTG Differential Pair | Integrated high-speed PHY enables direct connection to USB connectors without external transceiver. |
| CSPI1_MOSI/MISO/SCLK/SS | Configurable SPI Master Interface | Up to 52 Mbps operation; supports daisy-chained flash, sensors, or PMICs with hardware chip select. |
| GPIO1_0 | Power Ready Signal Input | Used to synchronize processor startup with PMIC rail stabilization; configurable as TX1 for alternate routing. |
Key Features
| Feature | Design Value |
|---|---|
| Image Processing Unit (IPUv1) | Hardware-accelerated color space conversion, rotation, scaling, and MPEG-4/H.264 post-filtering - eliminates CPU load for video pipeline tasks. |
| Asynchronous Sample Rate Converter (ASRC) | Supports concurrent audio sample rate conversion with –120 dB THD+N - enables multi-source audio mixing without jitter or resampling artifacts. |
| Secure JTAG Controller (SJC) | Enables authenticated debug access and prevents unauthorized firmware extraction - critical for certified industrial firmware deployments. |
| Enhanced Secure Digital Host Controller (eSDHCv2) | Supports SD, MMC, SDIO, and CE-ATA protocols - allows embedded storage expansion and wireless LAN via SDIO modules. |
| Advanced Power Management | Combines clock/power gating and well biasing to reduce subthreshold leakage by ~10× - extends battery life in portable HMIs and lowers thermal design power. |
Applications
| Industrial HMI Panel | Medical Display Terminal |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with real-time status visualization and alarm logging. IC Role / Device Role / Timing Role: Primary application processor executing Linux/QNX, driving 1024×1024 parallel RGB display, capturing button presses via KPP, and communicating over CAN bus to field devices. Use Value: Integrated IPU and GPU enable fluid SVG-based UI rendering and live camera feed overlay without external graphics IC, reducing BOM count and board area. | Use Scenario: Portable diagnostic device displaying ultrasound or endoscopic video with annotation and local storage. IC Role / Device Role / Timing Role: Video acquisition engine using parallel camera interface (30 Mpixels/s), real-time IPU-based deblocking, and HDMI/RGB output to medical-grade display. Use Value: On-chip ASRC and ESAI support synchronized multi-channel audio feedback while maintaining strict EMI compliance required in clinical environments. |
| Retail Self-Service Kiosk | Building Automation Gateway |
Use Scenario: Interactive kiosk with barcode scanner, receipt printer, and payment terminal interfacing via USB and serial ports. IC Role / Device Role / Timing Role: Central controller running Android/Linux, managing USB OTG peripheral enumeration, SDIO Wi-Fi module, and triple UARTs for legacy peripherals. Use Value: Dual SDIO/MMC + CE-ATA support enables simultaneous use of eMMC boot storage and removable SD card for firmware updates or audit logs. | Use Scenario: Protocol translator bridging BACnet MS/TP, Modbus RTU, and KNX to Ethernet/IP backbone. IC Role / Device Role / Timing Role: Real-time protocol stack executor leveraging dual CAN, Ethernet MAC, and GPIO-interrupt-driven fieldbus transceivers. Use Value: Integrated FlexCAN controllers with message RAM and FIFOs ensure deterministic response to HVAC actuator commands under heavy network load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multimedia applications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MCIMX353DJQ5C | Lacks OpenVG GPU and PATA interface; identical ARM1136 core, L2 cache, IPU, and peripheral set otherwise. | Suitable for cost-sensitive HMIs where 2D vector graphics acceleration is not required. | Select when GPU functionality is unnecessary and BOM cost reduction is prioritized over future UI scalability. |
| i.MX6ULL G0 | ARM Cortex-A7 @ 792 MHz, 128 KB L2 cache, Vivante GC7000UL GPU, no IPU; supports LVDS/eDP but no parallel camera interface. | Better suited for Linux-based GUIs with OpenGL ES, but lacks hardware video preprocessing for raw sensor streams. | Choose for next-generation designs needing higher CPU performance and modern GPU APIs, accepting trade-off in legacy camera/display interface support. |
Compared with MCIMX357DJQ5C, MCIMX353DJQ5C removes GPU and PATA while retaining identical power/performance envelope and industrial temperature rating; i.MX6ULL G0 offers higher CPU throughput and modern GPU but abandons IPU-based camera pipeline and parallel display support - making MCIMX357DJQ5C uniquely suited for legacy industrial imaging and HMI consolidation.
Availability
MCIMX357DJQ5C is available at Aetrix Electronics and suitable for industrial HMI panels, medical display terminals, retail self-service kiosks, and building automation gateways requiring stable component supply across extended product lifecycles.
Supply support for MCIMX357DJQ5C includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with roots in Freescale's embedded processor leadership.
The i.MX35 family was designed specifically for cost-sensitive industrial and consumer multimedia applications requiring ARM11-class performance, integrated graphics, and robust peripheral sets - targeting display controllers, HMIs, and portable media devices before the Cortex-A era.
FAQ
What is the maximum operating temperature range for the MCIMX357DJQ5C?
The MCIMX357DJQ5C is rated for industrial operation from –20°C to +70°C ambient temperature. This specification applies to silicon revision 2.1 in the MAPBGA-5284 package and is validated per Freescale's MCIMX35SR2CEC datasheet Rev. 10. Thermal derating is required above 70°C case temperature per Section 4.6.
Does the MCIMX357DJQ5C include an integrated graphics processing unit (GPU)?
Yes, the MCIMX357DJQ5C includes an OpenVG 1.1-compliant 2D graphics processing unit (GPU) as confirmed in Table 2 of the MCIMX35SR2CEC datasheet. This GPU accelerates vector graphics rendering and is absent in MCIMX351 and MCIMX353 variants, distinguishing the MCIMX357DJQ5C within the i.MX35 family.
Which memory types does the MCIMX357DJQ5C support via its external memory interface?
The MCIMX357DJQ5C supports SDRAM (up to 133 MHz), mobile DDR, DDR2 (4-bank architecture), SLC/MLC NAND Flash, NOR Flash, and SRAM through its External Memory Interface (EMI). These interfaces are detailed in Section 1 and Table 4 of the MCIMX35SR2CEC datasheet, enabling flexible boot and runtime memory configurations.
How many CAN interfaces are integrated into the MCIMX357DJQ5C?
The MCIMX357DJQ5C integrates two Controller Area Network (CAN) 2.0B interfaces, designated as FlexCAN modules. This capability is explicitly listed in Table 2 (Functional Differences) and Section 1.1 (Features) of the MCIMX35SR2CEC datasheet, supporting industrial fieldbus communication without external CAN controllers.
What package type and ball pitch does the MCIMX357DJQ5C use?
The MCIMX357DJQ5C uses a MAPBGA package (Case 5284), measuring 17 mm × 17 mm with 0.8 mm ball pitch. It is RoHS-compliant and lead-free, with Moisture Sensitivity Level (MSL) 3. The ball map corresponds to silicon revision 2.1, documented in Tables 95 and 97 of the MCIMX35SR2CEC datasheet.
MCIMX357DJQ5C Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 400-LFBGA
- Series:
- i.MX35
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM1136JF-S
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 532MHz
- Co-Processors/DSP:
- Multimedia; GPU, IPU, VFP
- RAM Controllers:
- LPDDR, DDR2
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- Keypad, KPP, LCD
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 + PHY (2)
- Voltage - I/O:
- 1.8V, 2.0V, 2.5V, 2.7V, 3.0V, 3.3V
- Operating Temperature:
- -20°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- Secure Fusebox, Secure JTAG, Tamper Detection
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 400-LFBGA (17x17)
- Additional Interfaces:
- 1-Wire, ASRC, ATA, CAN, I2C, I2S, MMC/SDIO, SAI, SPI, SSI, UART
MCIMX357DJQ5C FAQ
1.How can I place an order for MCIMX357DJQ5C through Aetrix?
Please submit a Request for Quotation (RFQ) for MCIMX357DJQ5C on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MCIMX357DJQ5C reliable?
The price and inventory of MCIMX357DJQ5C are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MCIMX357DJQ5C is usually 5 days.
3.What payment methods are accepted for MCIMX357DJQ5C?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MCIMX357DJQ5C transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MCIMX357DJQ5C?
MCIMX357DJQ5C orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MCIMX357DJQ5C order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MCIMX357DJQ5C?
For technical support, including MCIMX357DJQ5C datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MCIMX357DJQ5C requirements.
6.How does Aetrix verify that MCIMX357DJQ5C is sourced from the original manufacturer or authorized distributors?
All MCIMX357DJQ5C products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MCIMX357DJQ5C meets industry standards.
7.What is the process for return or replacement of MCIMX357DJQ5C?
All MCIMX357DJQ5C units undergo pre-shipment inspection (PSI). If there is an issue with MCIMX357DJQ5C, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MCIMX357DJQ5C part is unused and in its original packaging.
Return procedure for MCIMX357DJQ5C:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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