My Inquiry
My Account
NXP Semiconductors MCIMX6D5EYM10AER
- Part No.:
- MCIMX6D5EYM10AER
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 624-LFBGA, FCBGA
- Datasheet:
-
MCIMX6D5EYM10AER.pdf
- Description:
- IC MPU I.MX6D 1.0GHZ 624FCPBGA
- Quantity:
- Payment:
- Shipping:
Inventory:4,373
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MCIMX6D5EYM10AER from NXP Semiconductors is an industrial-grade i.MX 6Dual applications processor featuring dual Arm Cortex-A9 cores operating at 1.0 GHz, integrated VPU and GPU, 1 MB L2 cache, and support for DDR3/DDR3L/LPDDR2-800 memory. It delivers 1080p video decode/encode, OpenGL ES 2.0 3D graphics (200 MTri/s), and hardware-accelerated 2D/Vector graphics for embedded HMI and industrial control systems.
For engineers reviewing the MCIMX6D5EYM10AER datasheet, MCIMX6D5EYM10AER pinout, MCIMX6D5EYM10AER application, or MCIMX6D5EYM10AER equivalent, key selection considerations include industrial temperature range (−40°C to +105°C), FCPBGA-624 package with 0.8 mm pitch, dual-core performance under DVFS, secure boot via A-HAB v4, and interface concurrency limits across MIPI CSI-2, HDMI 1.4, and dual LVDS displays.
Technical Context
The MCIMX6D5EYM10AER implements a symmetric dual-core Arm Cortex-A9 MPCore platform with TrustZone, each core including 32 KB L1 instruction and data caches, NEON MPE co-processor, private timer, and watchdog. The SoC integrates a unified 1 MB L2 cache shared between both cores, SCU, GIC supporting 128 interrupts, and global timer.
It features dedicated hardware accelerators: VPU for H.264/VC-1/MPEG-4 1080p decode/encode; dual IPUv3H for image scaling, rotation, and overlay; GPU3Dv4 (OpenGL ES 2.0, 200 MTri/s); GPU2Dv2 for BitBLT/stretched BLT; GPUVGv2 for OpenVG 1.1 vector rendering; and ASRC for multi-channel asynchronous audio sample rate conversion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Architecture | Dual Arm Cortex-A9 r2p10 cores with TrustZone, NEON MPE, 32 KB L1 I/D cache per core |
| Max Operating Frequency | 1.0 GHz (industrial grade, confirmed in IMX6DQIEC Rev.6 Table 6) |
| L2 Cache | 1 MB unified instruction/data cache, shared by both cores |
| Memory Interface | 64-bit DDR3/DDR3L/LPDDR2-800 with interleaving support; up to DDR3-1066 timing |
| Graphics Acceleration | GPU3Dv4: OpenGL ES 2.0, 200 MTri/s, OpenCL support; GPU2Dv2: BitBLT/stretched BLT; GPUVGv2: OpenVG 1.1 |
| Video Processing | VPU supports 1080p30 H.264/VC-1/MPEG-4 decode & encode; dual IPUv3H for real-time image compositing |
| Security Features | A-HAB v4 (SHA-256, 2048-bit RSA), CAAM (16 KB secure RAM, NIST-certified PRNG), SNVS, CSU, TZ-enabled boot |
Pinout & Package
MCIMX6D5EYM10AER is housed in a 21 mm × 21 mm FCPBGA package with 624 balls and 0.8 mm pitch (lidded, RoHS-compliant). Pin assignments follow standardized signal naming per IMX6 Series Signal Name Map (EB792) and are documented in Section 6 of IMX6DQIEC Rev.6.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK_24M_IN | Primary Oscillator Input | Mandatory 24 MHz crystal input for USB PHY clocking and system boot; deviation > ±50 ppm invalidates USB operation |
| VDD_ARM | Core Power Supply | 1.1–1.3 V supply for Arm Cortex-A9 cores and L1/L2 caches; requires low-noise regulation and tight transient response |
| VDD_SOC | SoC Logic Power | 1.2–1.3 V supply for MMDC, GPC, CCM, and peripheral logic; decoupling critical for DDR timing stability |
| DDR_DQ[0:63] | DDR Data Bus | 64-bit bidirectional data bus for DDR3/DDR3L/LPDDR2; length-matched to <5 mm skew and routed with controlled impedance (40 Ω ±10%) |
| BOOT_MODE[1:0] | Boot Configuration | Pull-up/pull-down resistors define boot source (eMMC, NAND, SPI NOR, SD card); values latched at POR reset only |
Key Features
| Feature | Design Value |
|---|---|
| Smart Speed Technology | Dynamic voltage/frequency scaling (DVFS) enables full 1.0 GHz operation only when thermal headroom and workload demand exist; reduces average power by up to 40% vs fixed-frequency mode |
| Multi-Standard Video Codec | VPU hardware acceleration eliminates CPU load for 1080p30 decode/encode of H.264 BP/MP/HP, VC-1 AP, MPEG-4 ASP, and VP8 |
| Secure Boot Chain | A-HAB v4 enforces cryptographic verification of boot images using eFUSE-programmed 2048-bit RSA keys; prevents unauthorized firmware execution |
| Flexible Display Subsystem | Supports concurrent operation of HDMI 1.4 (up to 1080p60), dual LVDS (WUXGA@60Hz each), and parallel RGB (225 Mpixels/sec), with pixel-level composition in IPUv3H |
| Industrial Interface Set | Two FlexCAN 2.0B controllers (1 Mbps), Gigabit Ethernet (IEEE 1588), five UARTs (one RS485-capable), three I²C (400 kbps), and four PWM outputs with dead-time insertion |
Applications
| Industrial HMI Terminal | Medical Imaging Workstation |
|---|---|
Use Scenario: Rugged touchscreen panel in factory automation with real-time alarm display, recipe management, and remote diagnostics over EtherNet/IP. IC Role / Device Role / Timing Role: Primary application processor executing Linux RTOS, driving dual LVDS displays, processing CAN bus machine status, and managing encrypted firmware updates. Use Value: Dual Cortex-A9 cores handle UI rendering and protocol stack concurrently; VPU offloads JPEG/MPEG decoding for diagnostic image previews without CPU saturation. |
Use Scenario: Portable ultrasound device requiring real-time B-mode image acquisition, beamforming preprocessing, and HDMI output to clinical monitor. IC Role / Device Role / Timing Role: Central SoC coordinating MIPI CSI-2 sensor capture, GPU-accelerated image enhancement, and HDMI 1.4 streaming with sub-frame latency control. Use Value: Dual IPUv3H units perform simultaneous de-interlacing, gamma correction, and DICOM-compliant window/level adjustment at 30 fps; ASRC ensures clean audio feedback sync. |
| Railway Onboard Infotainment | Smart Energy Gateway |
Use Scenario: Passenger information system in train cars with live GPS-tracked maps, multilingual announcements, and emergency video streaming. IC Role / Device Role / Timing Role: Applications processor running Android Automotive OS, managing HDMI display, MIPI DSI secondary screen, GPS/Bluetooth/Wi-Fi coexistence, and secure OTA updates. Use Value: CAAM accelerates TLS 1.2 handshake for HTTPS-based content delivery; GPU3Dv4 renders smooth vector-based route animations at 60 fps on 1080p display. |
Use Scenario: DIN-rail mounted gateway aggregating Modbus RTU, DLMS/COSEM, and IEC 61850 data from substations and feeding cloud analytics via LTE. IC Role / Device Role / Timing Role: Secure edge node performing protocol translation, time-stamped event logging in SNVS RTC, and AES-256 encryption of metering data before transmission. Use Value: SNVS provides tamper-resistant real-time clock and secure non-volatile storage for audit logs; FlexCAN interfaces directly with legacy protection relays without external transceivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core industrial applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MCIMX6D7CVT08AC | 800 MHz max frequency, same FCPBGA-624 package, identical feature set except lower speed grade | Suitable for cost-sensitive designs where 1.0 GHz burst performance is unnecessary; thermal envelope reduced by ~15% | Select when sustained compute load remains below 70% and industrial temp range (−40°C to +105°C) is required |
| i.MX 8M Mini (NXP, MIMX8MM6CVTIZAB) | Quad Cortex-A53 + Cortex-M4, 1.8 GHz A53, 2 GB LPDDR4, integrated MIPI DSI/LVDS, no VPU but includes GC7000UL GPU | Better multimedia throughput and modern interface support (USB 3.0, PCIe), but higher BOM cost and different power sequencing | Choose for new designs needing future-proofing, AI inference (via M4), or higher-resolution display pipelines beyond 1080p |
Compared with MCIMX6D5EYM10AER, MCIMX6D7CVT08AC trades peak performance for lower power and cost while retaining identical security, display, and industrial interface capabilities; the i.MX 8M Mini offers architectural advancement and higher bandwidth but requires PCB redesign, new power delivery, and software migration effort.
Availability
MCIMX6D5EYM10AER is available at Aetrix Electronics and suitable for industrial HMI terminals, medical imaging workstations, railway infotainment systems, and smart energy gateways requiring stable component supply across extended lifecycle commitments.
Supply support for MCIMX6D5EYM10AER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The i.MX 6Dual series - including MCIMX6D5EYM10AER - was designed specifically for high-reliability industrial applications demanding long-term availability, extended temperature operation, and hardware-enforced security in resource-constrained environments.
FAQ
What is the maximum operating frequency of the MCIMX6D5EYM10AER and under what conditions is it guaranteed?
The MCIMX6D5EYM10AER is rated for 1.0 GHz operation across the full industrial temperature range (−40°C to +105°C junction), as specified in Table 6 of the IMX6DQIEC Rev.6 datasheet. This frequency is guaranteed only when using a 24 MHz input clock for USB functionality and adhering to the recommended power supply tolerances (VDD_ARM: 1.1–1.3 V, VDD_SOC: 1.2–1.3 V) and thermal management per Section 4.1.
Does the MCIMX6D5EYM10AER support secure boot, and what cryptographic standards does it implement?
Yes, the MCIMX6D5EYM10AER implements Advanced High Assurance Boot (A-HAB) v4 with SHA-256 hashing and 2048-bit RSA signature verification. It uses eFUSE-programmable keys, CAAM's NIST-certified PRNG, and SNVS-backed secure RTC to enforce chain-of-trust from ROM bootloader through OS kernel. All secure boot operations occur in hardware without software intervention.
Can the MCIMX6D5EYM10AER drive multiple displays simultaneously, and what combinations are supported?
Yes, the MCIMX6D5EYM10AER supports concurrent display output: one HDMI 1.4 port (up to 1080p60), two LVDS ports (each up to WUXGA@60Hz), one parallel RGB interface (225 Mpixels/sec), and MIPI DSI (2 lanes @ 1 Gbps). Total raw pixel throughput is capped at 450 Mpixels/sec (24 bpp), and active interface combinations must respect IOMUX pin multiplexing constraints defined in the reference manual.
What video codecs are accelerated by the VPU in the MCIMX6D5EYM10AER, and at what resolutions?
The VPU in MCIMX6D5EYM10AER provides hardware-accelerated decode and encode for H.264 (BP/MP/HP), VC-1 (AP), MPEG-4 (ASP), and VP8, all at up to 1080p30 resolution. It does not support HEVC/H.265 or AV1. Decode latency is ≤ 2 frame intervals; encode introduces ≤ 3 frame delay. Performance is independent of CPU load due to dedicated DMA and memory arbitration.
Is the MCIMX6D5EYM10AER pin-compatible with other i.MX 6Dual variants such as MCIMX6D7CVT08AC?
Yes, MCIMX6D5EYM10AER is pin-compatible with MCIMX6D7CVT08AC and all other i.MX 6Dual FCPBGA-624 variants (e.g., MCIMX6D5EYM10AD, MCIMX6D7CVT08AE). They share identical ball map, power sequencing requirements, and I/O voltage levels. Only frequency grade, temperature rating, and fuse configuration differ - enabling drop-in replacement in existing layouts with appropriate BIOS/firmware update.
MCIMX6D5EYM10AER Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 624-LFBGA, FCBGA
- Series:
- i.MX6D
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A9
- Number of Cores/Bus Width:
- 2 Core, 32-Bit
- Speed:
- 1.0GHz
- Co-Processors/DSP:
- Multimedia; NEON™ SIMD
- RAM Controllers:
- LPDDR2, LVDDR3, DDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- Keypad, LCD
- Ethernet:
- 10/100/1000Mbps (1)
- SATA:
- SATA 3Gbps (1)
- USB:
- USB 2.0 + PHY (4)
- Voltage - I/O:
- 1.8V, 2.5V, 2.8V, 3.3V
- Operating Temperature:
- -20°C ~ 105°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ, Boot Security, Cryptography, RTIC, Secure Fusebox, Secure JTAG, Secure Memory, Secure RTC, Tamper Detection
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 624-FCPBGA (21x21)
- Additional Interfaces:
- CAN, I2C, I2S, MMC/SD/SDIO, SAI, SPI, SSI, UART
MCIMX6D5EYM10AER FAQ
1.How can I place an order for MCIMX6D5EYM10AER through Aetrix?
Please submit a Request for Quotation (RFQ) for MCIMX6D5EYM10AER on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MCIMX6D5EYM10AER reliable?
The price and inventory of MCIMX6D5EYM10AER are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MCIMX6D5EYM10AER is usually 5 days.
3.What payment methods are accepted for MCIMX6D5EYM10AER?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MCIMX6D5EYM10AER transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MCIMX6D5EYM10AER?
MCIMX6D5EYM10AER orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MCIMX6D5EYM10AER order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MCIMX6D5EYM10AER?
For technical support, including MCIMX6D5EYM10AER datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MCIMX6D5EYM10AER requirements.
6.How does Aetrix verify that MCIMX6D5EYM10AER is sourced from the original manufacturer or authorized distributors?
All MCIMX6D5EYM10AER products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MCIMX6D5EYM10AER meets industry standards.
7.What is the process for return or replacement of MCIMX6D5EYM10AER?
All MCIMX6D5EYM10AER units undergo pre-shipment inspection (PSI). If there is an issue with MCIMX6D5EYM10AER, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MCIMX6D5EYM10AER part is unused and in its original packaging.
Return procedure for MCIMX6D5EYM10AER:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MCIMX6D5EYM10AER Tags
-
AT91SAM9260B-CU-999
Microchip Technology
-
AT91SAM9G25-CU
Microchip Technology
-
ATSAMA5D27C-CU
Microchip Technology
-
AT91SAM9X35-CU
Microchip Technology
-
AT91SAM9X25-CU
Microchip Technology
-
MCIMX6Y2CVM08AB
NXP Semiconductors
.JPG)
-
AM3352BZCZ100
Texas Instruments
-
AT91SAM9260B-CU
Microchip Technology
-
AT91SAM9260B-QU
Microchip Technology
-
ATSAMA5D31A-CU
Microchip Technology
-
AT91SAM9G20B-CU-999
Microchip Technology
-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
