NXP Semiconductors MCIMX6S5EVM10AC

Overview

MCIMX6S5EVM10AC from NXP Semiconductors is an i.MX 6Solo applications processor featuring a single Arm Cortex-A9 core operating at 1 GHz, integrated VPU and GPU for multimedia acceleration, no EPDC (E-Ink Display Controller), and extended commercial temperature range (–20°C to +105°C). It implements DDR3/DDR3L/LPDDR2-800 memory interface, dual CAN, Gigabit Ethernet, HDMI 1.4, MIPI CSI-2/DSI, and USB 2.0 OTG + three HS hosts - deployed in portable medical devices and industrial HMIs.

For engineers reviewing the MCIMX6S5EVM10AC datasheet, MCIMX6S5EVM10AC pinout, MCIMX6S5EVM10AC application, or MCIMX6S5EVM10AC equivalent, key selection considerations include its 21 mm × 21 mm MAPBGA package with 0.8 mm pitch, absence of EPDC, extended temperature rating, and confirmed support for DVFS, TrustZone, and CAAM-based cryptographic acceleration.

Technical Context

The MCIMX6S5EVM10AC implements a symmetric Arm Cortex-A9 MPCore platform with 32 KB L1 instruction and data caches, 512 KB unified L2 cache, NEON MPE co-processor, and TrustZone security extensions. Its memory subsystem supports 16/32-bit DDR3-800, DDR3L-800, and LPDDR2-800 with interleaving capability.

Peripherals include dual FlexCAN controllers (1 Mbps), Gigabit Ethernet MAC (IEEE 1588 compliant, 400 Mbps real-world throughput), HDMI 1.4 transmitter, two MIPI CSI-2 lanes (up to 1 Gbps/lane), and four uSDHC ports supporting UHS-I SDR-104 (104 MB/s). Power management integrates DVFS, SW state retention, and hardware-accelerated clock gating.

Key Specifications

Pinout & Package

MCIMX6S5EVM10AC uses a 484-ball MAPBGA package (21 mm × 21 mm, 0.8 mm pitch), designated BGA Case 2240 per NXP documentation. Ball map and signal assignments are defined in Section 6.2 of IMX6SDLCEC Rev. 9.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar applications processor applications.

Compared with MCIMX6S5DVM10AC, the MCIMX6S5EVM10AC provides verified operation at –20°C startup and +105°C steady-state, enabling deployment in outdoor kiosks and industrial cabinets without derating. Against MCIMX6U5EVM10AC, it delivers identical security, multimedia, and interface capabilities at lower BOM cost and thermal envelope - ideal for single-display, single-task embedded systems.

Availability

MCIMX6S5EVM10AC is available at Aetrix Electronics and suitable for portable medical devices, industrial HMIs, IP video intercoms, and energy management gateways requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for MCIMX6S5EVM10AC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer markets.

The i.MX 6Solo family - including MCIMX6S5EVM10AC - was designed specifically for cost-sensitive, power-constrained embedded applications requiring rich multimedia, real-time connectivity, and hardware-enforced security in extended temperature environments.

FAQ

What is the maximum DDR3 memory speed supported by MCIMX6S5EVM10AC?

The MCIMX6S5EVM10AC supports DDR3-800 (400 MHz clock) with CL6 timing, delivering up to 12.8 GB/s peak bandwidth across its 32-bit interface. This is validated for 16/32-bit configurations with DDR3L and LPDDR2-800 as specified in Section 4.2 of IMX6SDLCEC Rev. 9. The MCIMX6S5EVM10AC does not support DDR4 or LPDDR3.

Does MCIMX6S5EVM10AC include hardware support for secure boot?

Yes, MCIMX6S5EVM10AC implements Advanced High Assurance Boot (A-HAB v4) with SHA-256 hashing, 2048-bit RSA signature verification, and eFUSE-based key storage. Secure boot flow is enforced by the Boot ROM and CSU, validating signed bootloader images before releasing the Cortex-A9 core from reset - all documented in the i.MX 6Solo Security Reference Manual.

Can MCIMX6S5EVM10AC drive both HDMI and LVDS displays simultaneously?

Yes, MCIMX6S5EVM10AC supports concurrent HDMI 1.4 and LVDS output via separate display pipelines - confirmed in Section 6.1 of IMX6SDLCEC Rev. 9. The HDMI port handles up to 1080p60, while dual LVDS lanes support WUXGA (1920×1200) at 60 Hz, with independent pixel clocks and timing generators.

What is the functional difference between MCIMX6S5EVM10AC and MCIMX6S5EVM10AD?

The sole difference is packaging: MCIMX6S5EVM10AC uses a standard MAPBGA with lead-free (Pb-free) finish, while MCIMX6S5EVM10AD employs a halogen-free, lead-free MAPBGA. Both share identical silicon, temperature rating (–20°C to +105°C), features, pinout, and electrical specifications per Table 1 of IMX6SDLCEC Rev. 9.

Does MCIMX6S5EVM10AC integrate an E-Ink Display Controller (EPDC)?

No, MCIMX6S5EVM10AC explicitly excludes the EPDC module, as indicated by the "5" in its part number nomenclature (per Figure 1, page 5 of IMX6SDLCEC Rev. 9). Models with EPDC carry "8" (e.g., MCIMX6S8EVM10AC). This omission reduces die size and power consumption, making MCIMX6S5EVM10AC optimal for non-E-Ink applications.