Microchip Technology MCP23017-E/ML

Overview

MCP23017-E/ML from Microchip Technology is a 16-bit I²C-compatible I/O expander IC with dual 8-bit ports (PORTA and PORTB), supporting 1.8V–5.5V operation, 1.7 MHz high-speed I²C interface, and configurable interrupt outputs (INTA/INTB). It provides bidirectional GPIO control, internal weak pull-ups (75 µA typical at 5V), and hardware address pins (A0–A2) for up to eight devices on one bus - used in microcontroller peripheral expansion for industrial HMI, sensor node aggregation, and embedded control panels.

For engineers reviewing the MCP23017-E/ML datasheet, MCP23017-E/ML pinout, MCP23017-E/ML application, or MCP23017-E/ML equivalent, key selection considerations include I²C speed mode support (100 kHz / 400 kHz / 1.7 MHz), interrupt configuration flexibility (active-high/low/open-drain), GPA7/GPB7 output-only limitation, thermal pad handling (EP pin), and register-level bank addressing (IOCON.BANK).

Technical Context

The MCP23017-E/ML implements a dual-register bank architecture (BANK = 0 or 1) governing address mapping for its 22 registers, including IODIR, GPIO, OLAT, IPOL, GPINTEN, and IOCON. Its I²C interface uses standard 7-bit addressing with three hardware-configurable bits (A0–A2), enabling multi-device bus topology without software arbitration.

Interrupt logic supports two independent sources per port: interrupt-on-change from default register state or from user-defined DEFVAL comparison. The INTA/INTB outputs can be configured as separate signals or OR'ed via MIRROR bit, with glitch filtering (150 ns) and capture registers (INTCAP) preserving port state at interrupt assertion.

Key Specifications

Pinout & Package

Package: 28-pin QFN (6 × 6 mm body) with exposed thermal pad (EP). Pin 29 (EP) must be connected to VSS or left unconnected per layout guidelines.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I/O expander applications.

Compared with PCA9555D,118 and TCA6424ARGJR, the MCP23017-E/ML uniquely combines AEC-Q100 qualification, 1.7 MHz I²C speed, full 3-bit hardware addressing, and dual-interrupt coalescing - making it optimal for automotive and industrial designs demanding timing determinism and bus scalability.

Availability

MCP23017-E/ML is available at Aetrix Electronics and suitable for industrial HMI panels, multi-sensor gateways, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for MCP23017-E/ML includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and connectivity solutions, serving industrial, automotive, and consumer markets with high-reliability silicon and development tools.

The MCP23017-E/ML belongs to Microchip's MCP23X17 family of serial I/O expanders, designed specifically to relieve GPIO resource pressure in embedded systems while maintaining deterministic interrupt response and flexible voltage interoperability.

FAQ

What is the maximum I²C clock frequency supported by the MCP23017-E/ML?

The MCP23017-E/ML supports three I²C speed modes: 100 kHz (standard mode), 400 kHz (fast mode), and 1.7 MHz (high-speed mode). The 1.7 MHz mode requires VDD ≥ 4.5V and operates within –40°C to +125°C ambient range. This allows the MCP23017-E/ML to deliver faster register read/write throughput than legacy expanders, reducing host MCU I/O overhead in time-sensitive applications.

Can GPA7 and GPB7 be used as inputs on the MCP23017-E/ML?

No - GPA7 and GPB7 are output-only pins on the MCP23017-E/ML, as confirmed in the datasheet's Pin Descriptions table (DS20001952D-page 11). While other GPA0–GPA6 and GPB0–GPB6 pins support full bidirectional operation with interrupt-on-change and internal pull-up enablement, GPA7/GPB7 lack input buffer circuitry and must be configured as outputs only. This limitation applies specifically to the MCP23017-E/ML and is not present in SPI variants like MCP23S17.

How does the MCP23017-E/ML handle interrupt coalescing between PORTA and PORTB?

The MCP23017-E/ML supports interrupt coalescing via the MIRROR bit in the IOCON register. When MIRROR = 1, INTA and INTB are logically OR'ed, causing either port's interrupt condition to assert both outputs simultaneously. When MIRROR = 0, INTA responds only to PORTA events and INTB only to PORTB events. This gives designers flexibility to implement either segregated or unified interrupt handling - a feature absent in simpler expanders like the PCF8574.

Is the exposed thermal pad (EP) on the MCP23017-E/ML package required to be connected?

The exposed thermal pad (Pin 29) on the MCP23017-E/ML QFN package may be connected to VSS or left unconnected, per Microchip's layout guidance in DS20001952D-page 11. Connecting EP to VSS improves thermal dissipation and reduces junction temperature under sustained 25 mA per-pin loading, but is not mandatory for functional operation at room temperature and moderate duty cycles. PCB design must ensure solder mask clearance around EP to avoid shorting.

Does the MCP23017-E/ML support automatic register address incrementing during I²C transfers?

Yes - the MCP23017-E/ML supports automatic address pointer incrementing in Sequential mode (IOCON.SEQOP = 0, default), allowing multi-byte reads/writes without retransmitting register addresses. In Byte mode (IOCON.SEQOP = 1), the address pointer remains fixed, enabling efficient polling of GPIO registers or repeated writes to OLAT latches. This dual-mode capability is explicitly documented in Section 3.2.1 of the datasheet and distinguishes the MCP23017-E/ML from expanders with fixed-address protocols.