Microchip Technology MCP23S17T-E/SO

Overview

MCP23S17T-E/SO from Microchip Technology is a 16-bit SPI-based I/O expander IC designed for embedded microcontroller systems requiring scalable parallel port expansion. It provides two 8-bit bidirectional ports (PORTA and PORTB), supports 10 MHz SPI operation at 2.7–5.5V, features dual configurable interrupt outputs (INTA/INTB), and operates across –40°C to +85°C industrial temperature range - used in industrial HMI panels for GPIO extension of ARM Cortex-M hosts.

For engineers reviewing the MCP23S17T-E/SO datasheet, MCP23S17T-E/SO pinout, MCP23S17T-E/SO application, or MCP23S17T-E/SO equivalent, key selection criteria include SPI interface compatibility, 16-bit I/O configurability per port, interrupt source flexibility (change vs. default-matching), hardware address pin support (A0–A2), and SOIC-28 package suitability for through-hole or reflow assembly.

Technical Context

The MCP23S17T-E/SO implements a register-mapped SPI peripheral with 22 control/status registers organized in BANK=0 (16-register linear map) or BANK=1 (port-segregated addressing). Its GPIO architecture supports independent direction, polarity, pull-up, interrupt-on-change, and default-value configuration per pin.

Interrupt logic allows INTA/INTB to operate independently or as a wired-OR pair, with glitch filtering (150 ns) and interrupt capture latching. The device uses Schmitt-trigger inputs on CS, RESET, SCK, and SI, and includes internal weak pull-ups (40–115 µA at 5V) configurable per port pin.

Key Specifications

Pinout & Package

Package: 28-pin SOIC, wide body (7.50 mm), RoHS-compliant, surface-mount or through-hole compatible.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I/O expansion applications.

Compared with MCP23017T-E/SO and TCA9554APWR, the MCP23S17T-E/SO uniquely delivers 16-bit SPI expandability with dual interrupt outputs, glitch filtering, and interrupt capture - making it optimal for deterministic, low-latency, and noise-immune embedded I/O extension.

Availability

MCP23S17T-E/SO is available at Aetrix Electronics and suitable for industrial automation, automotive electronics, and medical device applications requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.

Supply support for MCP23S17T-E/SO includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontroller, analog, FPGA, and connectivity solutions, serving industrial, automotive, communications, and consumer markets since 1989.

The MCP23X17 product line was designed specifically for scalable, low-overhead parallel I/O expansion in resource-constrained embedded systems - emphasizing register-level configurability, interrupt efficiency, and multi-voltage interoperability.

FAQ

What is the maximum SPI clock frequency supported by the MCP23S17T-E/SO?

The MCP23S17T-E/SO supports up to 10 MHz SPI clock frequency when operated at 2.7–5.5V supply voltage. At 1.8–2.7V, the maximum is 5 MHz. This specification is verified in Table 1-4 of the DS20001952D datasheet under "Clock Frequency" with test conditions explicitly stated for each voltage range. The MCP23S17T-E/SO achieves this speed using optimized internal serialization logic and Schmitt-triggered inputs for noise immunity.

Does the MCP23S17T-E/SO support both SPI Mode 0,0 and Mode 1,1?

Yes, the MCP23S17T-E/SO supports both SPI Mode 0,0 (CPOL=0, CPHA=0) and Mode 1,1 (CPOL=1, CPHA=1), as confirmed in Figure 1-5 and Figure 1-6 of the DS20001952D datasheet. When using Mode 1,1, the datasheet specifies that the CS pin must be toggled once before the first communication after power-up to initialize internal state correctly - a requirement unique to that mode.

How many devices can be connected on a single SPI bus using the MCP23S17T-E/SO?

Up to eight MCP23S17T-E/SO devices can be connected on a single SPI bus using the A0, A1, and A2 hardware address pins. These pins configure a 3-bit address when IOCON.HAEN = 1. Each device must have a unique combination of A0–A2 biasing (VDD or VSS), and CS lines remain independent - enabling multi-drop SPI without address collisions or protocol arbitration.

What is the purpose of the INTA and INTB pins on the MCP23S17T-E/SO?

The INTA and INTB pins on the MCP23S17T-E/SO provide asynchronous interrupt signaling for PORTA and PORTB, respectively. They can be configured independently as active-high, active-low, or open-drain outputs, and may be logically OR'ed together via IOCON.MIRROR. Their activation is triggered by GPIO state changes or DEFVAL register mismatches - enabling efficient event-driven firmware without continuous polling of the MCP23S17T-E/SO GPIO registers.

Is the MCP23S17T-E/SO pin-compatible with the MCP23017T-E/SO?

No, the MCP23S17T-E/SO is not pin-compatible with the MCP23017T-E/SO despite sharing the same SOIC-28 package and nearly identical pin functions. Key differences include NC/CS (pin 11) versus SDA (pin 13), and NC/SO (pin 14) versus SCL (pin 12) - reflecting their distinct SPI and I²C interface requirements. PCB layout must be redesigned to route CS, SCK, SI, and SO instead of SDA and SCL.