Microchip Technology MIC2810-1J6SYML-TR
- Part No.:
- MIC2810-1J6SYML-TR
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-VFQFN
- Datasheet:
-
MIC2810-1J6SYML-TR.pdf
- Description:
- DC-DC + 2 LINEAR REGULATORS WITH
- Quantity:
- Payment:

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Product details
Overview
MIC2810-1J6SYML-TR from Microchip Technology is a digital power management IC integrating a 2 MHz, 600 mA DC/DC buck converter and two independent 300 mA LDOs (LDO1: 1.4 V, LDO2: 3.3 V), all with individual enable control and LOWQ ultra-low-noise light-load mode. It delivers <30 µA total quiescent current in LOWQ mode, 53 µVRMS DC/DC output noise, and operates across –40°C to +125°C for embedded MPU power in portable and RF-sensitive systems.
For engineers reviewing the MIC2810-1J6SYML-TR datasheet, MIC2810-1J6SYML-TR pinout, MIC2810-1J6SYML-TR application, or MIC2810-1J6SYML-TR equivalent, this page provides verified specifications, validated pin functions, confirmed thermal and noise performance in both PWM and LOWQ modes, and real-world sequencing behavior for backup-power-aware designs.
Technical Context
The MIC2810-1J6SYML-TR implements a dual-mode regulation architecture: full-power 2 MHz PWM operation for high-efficiency 600 mA loads, and LOWQ linear-mode operation where the DC/DC is disabled and output is sourced via LDO path with 53 µVRMS noise and <30 µA IQ. Its POR circuit uses a programmable CSET capacitor to set delay time (up to 1 s) and performs logic-OR monitoring across all three outputs.
Pin-level isolation enables leakage-free interfacing with host MPUs under backup power: the open-drain POR output lacks clamping diodes to supply rails, allowing safe pull-up to auxiliary domains; EN/EN1/EN2 are CMOS inputs requiring ≥1.0 V logic high, while LOWQ is active-low with defined 0.2 V/1.0 V thresholds. Thermal shutdown activates at 160°C with 23°C hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | VIN/VIN2: 2.7–5.5 V; VIN1: 1.65–5.5 V - supports wide-input battery and rail-sourced systems with LDO1 usable from low-voltage sources. |
| DC/DC Output Current | 600 mA in PWM mode - sufficient for core MPU voltage rails; reduced to 60 mA in LOWQ mode for ultra-low-noise standby. |
| LDO Output Current | LDO1/LDO2: 300 mA each - enables independent powering of I/O, memory, or RF subsystems with tight load regulation (≤0.4% up to 300 mA). |
| Quiescent Current | 30 µA total in LOWQ mode - extends battery life in always-on wearable or sensor nodes without compromising POR functionality. |
| Output Noise | 53 µVRMS (DC/DC, LOWQ mode); 91 µVRMS (LDOs) - enables direct powering of RF transceivers and precision analog circuits without additional filtering. |
| Package | 16-pin 3 mm × 3 mm QFN - compact footprint with separate SGND/PGND pins for optimal noise separation in mixed-signal layouts. |
| Operating Temperature | –40°C to +125°C - qualified for industrial and automotive under-hood applications requiring extended thermal robustness. |
Pinout & Package
Package: 16-pin, 3 mm × 3 mm, 0.85 mm height, leadless QFN (ML suffix), exposed thermal pad, Pb-free.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 (LOWQ) | Mode Control Input | Active-low logic input selecting PWM (HIGH) or LOWQ linear (LOW); defines system-wide power state and noise profile. |
| 2 (BIAS) | Internal Bias Supply | Powers internal reference/control circuitry via 6 Ω internal resistor; requires 0.1 µF bypass to SGND for stability. |
| 3 (SGND) | Signal Ground Reference | Low-current return path for bias, POR, and enable logic; must be routed separately from PGND to avoid noise coupling. |
| 4 (PGND) | Power Ground Return | High-current return for DC/DC switch node; connects directly to inductor and input/output capacitors' ground planes. |
| 5 (SW) | Switch Node Output | Drives external inductor in PWM mode; high-impedance in LOWQ mode; requires short, low-inductance PCB trace. |
| 6 (VIN) | Main Power Input | Supplies DC/DC controller, reference, and shared circuitry; must be connected to Pin 7 (VIN2) and decoupled with 4.7 µF ceramic. |
| 7 (VIN2) | LDO2 Input Supply | Provides input to LDO2; tied to VIN (Pin 6) per datasheet; minimum 2.7 V required. |
| 8 (LDO2) | LDO2 Regulated Output | Fixed 3.3 V output (per part number suffix '1J6S'); requires ≥2.2 µF ceramic output capacitor for stability. |
| 9 (LDO) | LDO Output Path | Connects to DC/DC output node; supplies regulated voltage to load in LOWQ mode; disables during PWM operation. |
| 10 (VIN1) | LDO1 Input Supply | Supplies LDO1; supports down to 1.65 V - enables use with partially discharged batteries or low-voltage rails. |
| 11 (LDO1) | LDO1 Regulated Output | Fixed 1.4 V output (per '1J6S'); powers low-voltage cores or I/O; shares same capacitor requirements as LDO2. |
| 12 (POR) | Open-Drain Reset Flag | Asserts low if any output (DC/DC, LDO1, LDO2) falls out of regulation; no clamping diodes - safe for backup-domain interfacing. |
| 13 (CSET) | POR Delay Timing | Current source (1.25 µA typ.) charging external capacitor; delay = CSET (pF) in µs; sets POR assertion timing after startup or enable transitions. |
| 14 (EN1) | LDO1 Enable | Active-high CMOS input; controls LDO1 independently; floating prohibited; <1 µA shutdown current when low. |
| 15 (EN) | DC/DC Enable | Active-high CMOS input; enables/disables buck regulator; tri-states SW node when disabled to prevent backfeed. |
| 16 (EN2) | LDO2 Enable | Active-high CMOS input; controls LDO2 independently; supports staggered power sequencing with POR coordination. |
Key Features
| Feature | Design Value |
|---|---|
| LOWQ Ultra-Low-Noise Mode | Reduces total IQ to <30 µA while delivering clean 53 µVRMS DC/DC output - eliminates PFM ripple interference in RF receivers. |
| Independent Triple-Output Control | Separate EN, EN1, EN2 pins allow precise sequencing of DC/DC, LDO1 (1.4 V), and LDO2 (3.3 V) - critical for multi-rail MPU boot order. |
| Backup-Power-Safe POR | Open-drain POR output with no rail-clamping diodes enables reliable reset assertion even when main supply is off and backup domain is active. |
| Thermal & Current Protection | Integrated thermal shutdown (160°C, 23°C hysteresis) and cycle-by-cycle current limiting (1.6 A PWM / 190 mA LOWQ) ensure robust fault handling. |
| Small External Components | Optimized for 2.2 µH inductor and 2.2 µF ceramic output capacitors on all rails - minimizes board area and BOM count. |
Applications
| Embedded MPU Core Power | Portable RF Transceiver Supply |
|---|---|
|
Use Scenario: Powering ARM Cortex-A/M series application processors with dynamic voltage scaling and deep-sleep states. IC Role / Device Role / Timing Role: Provides primary core voltage (DC/DC, 1.25 V), I/O voltage (LDO1, 1.4 V), and RF bias (LDO2, 3.3 V) with coordinated enable sequencing. Use Value: LOWQ mode maintains sub-30 µA system standby while preserving POR integrity and enabling instant wake-up without LDO-to-DC/DC handoff delay. |
Use Scenario: Supplying Bluetooth/Wi-Fi SoCs in wearables where RF sensitivity demands ultra-low switching noise. IC Role / Device Role / Timing Role: Delivers clean 3.3 V to RF front-end via LDO2 while DC/DC powers baseband; LOWQ mode silences DC/DC during receive windows. Use Value: 53 µVRMS DC/DC noise in LOWQ mode prevents desensitization of RF receivers - eliminating need for extra ferrite beads or LC filters. |
| Industrial Sensor Node Backup Power | Multi-Rail Sequencing for FPGA I/O Banks |
|
Use Scenario: Maintaining real-time clock, SRAM, and sensor interface during main supply brownout or battery swap. IC Role / Device Role / Timing Role: Uses POR flag to trigger backup switchover; LDO1 (1.4 V) powers RTC, LDO2 (3.3 V) powers sensor interface, all while drawing <30 µA. Use Value: POR's rail-agnostic open-drain output allows pull-up to backup rail - ensuring reset signaling remains valid even when main VIN is absent. |
Use Scenario: Powering Xilinx/Intel FPGA banks requiring strict voltage ramp order (VCCINT before VCCIO before VCCAUX). IC Role / Device Role / Timing Role: Enables staggered activation via EN/EN1/EN2 with CSET-programmed POR delay to enforce timing margins between rail startups. Use Value: Programmable POR delay (up to 1 s) ensures all rails reach regulation before releasing system reset - preventing FPGA configuration failure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-output PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIC2810-4GSYML-TR | Fixed outputs: 1.2 V / 1.8 V / 3.3 V - differs in DC/DC and LDO1 voltages; identical package, pinout, and LOWQ/POR architecture. | Suitable for designs requiring 1.2 V core and 1.8 V I/O instead of 1.25 V / 1.4 V; same sequencing and noise performance. | Select when matching existing 1.2 V/1.8 V/3.3 V reference design; no layout change needed - pin-compatible drop-in replacement. |
| TPS65023BRSBR | Triple-output PMIC (2 buck + 1 LDO), 2.25–6.5 V input, but no LOWQ mode; higher IQ (80 µA typical), 120 µVRMS noise; 24-pin QFN. | Lacks ultra-low-noise light-load capability; better suited for non-RF applications with higher input voltage range and higher current demands. | Choose when input exceeds 5.5 V or >600 mA DC/DC current is required; not suitable for RF-sensitive or sub-30 µA standby designs. |
Compared with MIC2810-4GSYML-TR, the MIC2810-1J6SYML-TR provides tighter core voltage (1.25 V vs. 1.2 V) and lower I/O voltage (1.4 V vs. 1.8 V), optimizing power for newer low-VT processors; versus TPS65023BRSBR, it delivers 44% lower quiescent current and 56% lower output noise - critical for battery-constrained RF systems.
Availability
MIC2810-1J6SYML-TR is available at Aetrix Electronics and suitable for embedded MPU power, portable RF transceiver supply, and industrial sensor node backup power requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for MIC2810-1J6SYML-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global provider of microcontrollers, analog components, and power management ICs, with emphasis on reliability, longevity, and industrial-grade qualification.
The MIC2810 product line delivers integrated, sequenced, and low-noise power solutions for resource-constrained embedded systems - specifically engineered for battery-powered, RF-sensitive, and thermally demanding applications.
FAQ
What output voltages does the MIC2810-1J6SYML-TR provide?
The MIC2810-1J6SYML-TR delivers three fixed output voltages: 1.25 V from the DC/DC converter, 1.4 V from LDO1, and 3.3 V from LDO2 - as confirmed by Microchip's Product Identification System ('1J6S' suffix). All outputs are independently enabled and support precise sequencing via dedicated EN pins.
How does the LOWQ mode affect the DC/DC converter and LDOs in the MIC2810-1J6SYML-TR?
In LOWQ mode (LOWQ pin ≤ 0.2 V), the MIC2810-1J6SYML-TR disables the DC/DC PWM circuitry and routes output through the LDO path, reducing total quiescent current to <30 µA and lowering DC/DC output noise to 53 µVRMS. LDO1 and LDO2 current limits are reduced to <50 mA each, and the SW pin becomes high-impedance.
Can the MIC2810-1J6SYML-TR POR output be safely pulled up to a backup power rail?
Yes - the MIC2810-1J6SYML-TR POR pin is an open-drain output with no internal clamping diodes to VIN or other supplies, enabling direct pull-up to a backup domain (e.g., coin cell or supercap) without parasitic leakage. This ensures valid reset signaling even when main power is removed.
What is the purpose of the CSET pin on the MIC2810-1J6SYML-TR, and how is it configured?
The CSET pin on the MIC2810-1J6SYML-TR sources a 1.25 µA current to charge an external capacitor to 1.25 V, setting the POR assertion delay time in microseconds equal to the capacitor value in picofarads (e.g., 100 nF = 100,000 pF = 100,000 µs delay). Leaving CSET open yields minimum delay; grounding is prohibited.
Does the MIC2810-1J6SYML-TR support independent enable control for all three regulators?
Yes - the MIC2810-1J6SYML-TR provides fully independent enable control: EN for the DC/DC converter, EN1 for LDO1, and EN2 for LDO2. Each is an active-high CMOS input with defined logic thresholds (VIH ≥ 1.0 V, VIL ≤ 0.2 V), and all must be actively driven - floating is prohibited per datasheet guidance.
MIC2810-1J6SYML-TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 16-VFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) (1), Linear (LDO) (2)
- Number of Outputs:
- 3
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- 1.25V, 600mA
- Voltage/Current - Output 2:
- 1.4V, 300mA
- Voltage/Current - Output 3:
- 3.3V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QFN (3x3)
MIC2810-1J6SYML-TR FAQ
1.How can I place an order for MIC2810-1J6SYML-TR through Aetrix?
Please submit a Request for Quotation (RFQ) for MIC2810-1J6SYML-TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIC2810-1J6SYML-TR reliable?
The price and inventory of MIC2810-1J6SYML-TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIC2810-1J6SYML-TR is usually 5 days.
3.What payment methods are accepted for MIC2810-1J6SYML-TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIC2810-1J6SYML-TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIC2810-1J6SYML-TR?
MIC2810-1J6SYML-TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIC2810-1J6SYML-TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIC2810-1J6SYML-TR?
For technical support, including MIC2810-1J6SYML-TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIC2810-1J6SYML-TR requirements.
6.How does Aetrix verify that MIC2810-1J6SYML-TR is sourced from the original manufacturer or authorized distributors?
All MIC2810-1J6SYML-TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIC2810-1J6SYML-TR meets industry standards.
7.What is the process for return or replacement of MIC2810-1J6SYML-TR?
All MIC2810-1J6SYML-TR units undergo pre-shipment inspection (PSI). If there is an issue with MIC2810-1J6SYML-TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIC2810-1J6SYML-TR part is unused and in its original packaging.
Return procedure for MIC2810-1J6SYML-TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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