Microchip Technology MIC2810-4GMYML-TR
- Part No.:
- MIC2810-4GMYML-TR
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-VQFN Exposed Pad, 16-MLF®
- Datasheet:
-
MIC2810-4GMYML-TR.pdf
- Description:
- IC REG TRPL BUCK/LNR 2MHZ 16MLF
- Quantity:
- Payment:

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Product details
Overview
MIC2810-4GMYML-TR from Microchip Technology is a digital power management IC integrating a 2 MHz, 600 mA DC/DC buck converter and two independent 300 mA LDOs (LDO1 and LDO2) with output voltages of 1.2 V, 1.8 V, and 2.8 V respectively. It features LOWQ mode for ultra-low-noise operation at 30 µA quiescent current, integrated power-on reset (POR) with programmable delay, and thermal/current protection. It powers embedded MPU subsystems requiring tightly sequenced, low-noise, multi-rail supplies.
For engineers reviewing the MIC2810-4GMYML-TR datasheet, MIC2810-4GMYML-TR pinout, MIC2810-4GMYML-TR application, or MIC2810-4GMYML-TR equivalent, key selection considerations include its triple-output architecture, 3 mm × 3 mm QFN package, LOWQ vs. PWM mode trade-offs (53 µVRMS noise vs. >90% efficiency), and POR sequencing control via CSET capacitor.
Technical Context
The MIC2810-4GMYML-TR implements a dual-mode regulation architecture: in LOWQ mode (LOWQ = GND), the DC/DC converter is disabled and replaced by an LDO-based output path delivering up to 60 mA with 53 µVRMS noise; in full-power mode (LOWQ = VIN), the 2 MHz PWM converter delivers up to 600 mA with >90% efficiency. The device uses separate input pins (VIN, VIN1, VIN2) to support wide input ranges: 2.7–5.5 V for VIN/VIN2 and 1.65–5.5 V for VIN1.
Its POR output is open-drain and logic-OR'd across all three regulated outputs, with delay programmable via external capacitor on CSET (1.25 µA current source, delay = CSET in pF). All enable inputs (EN, EN1, EN2) are CMOS-compatible active-high signals with <1 µA shutdown current when all are deasserted.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | VIN/VIN2: 2.7–5.5 V; VIN1: 1.65–5.5 V - enables flexible rail sourcing including single-cell Li-ion or backup domains. |
| DC/DC Output Current | 600 mA (PWM mode); 60 mA (LOWQ mode) - supports dynamic load scaling between high-efficiency switching and ultra-low-noise linear regulation. |
| LDO1/LDO2 Output Current | 300 mA each - sufficient for core logic, I/O, or RF bias rails in portable systems. |
| Quiescent Current | 30 µA total in LOWQ mode - extends battery life in always-on, low-duty-cycle applications like wearables. |
| Output Noise (DC/DC) | 53 µVRMS (10 Hz–100 kHz, LOWQ mode) - avoids interference with sensitive RF receivers or precision analog circuits. |
| Switching Frequency | 2 MHz (±10%) - allows use of small 2.2 µH inductors and 2.2 µF ceramic capacitors, minimizing board area. |
| POR Delay Programmability | CSET pin accepts external capacitor; delay = CSET value in picofarads (e.g., 100 nF → 100 ms) - enables precise power-up sequencing across multiple voltage domains. |
Pinout & Package
The MIC2810-4GMYML-TR is housed in a 16-pin, 3 mm × 3 mm, 0.85 mm-thick QFN package with exposed thermal pad (PGND-connected). Pin 1 is marked by a dot; SGND and PGND are separate ground paths for signal integrity and thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LOWQ (Pin 1) | Mode select input | Active-low control: GND enables ultra-low-noise LDO-only mode (30 µA IQ); VIN enables full-power 2 MHz PWM mode (600 mA). |
| BIAS (Pin 2) | Bias supply input | Powers internal reference/control circuitry via internal 6 Ω resistor; requires 0.1 µF bypass to SGND. |
| SGND (Pin 3) | Signal ground | Return path for low-current analog/digital control circuitry; must be routed separately from PGND to avoid noise coupling. |
| PGND (Pin 4) | Power ground | High-current return for DC/DC switch node (SW); connects to thermal pad for heat dissipation. |
| SW (Pin 5) | Switch node output | Drives external inductor; high dv/dt node requiring short, shielded routing away from sensitive traces. |
| VIN (Pin 6) | Main supply input | Primary input for DC/DC controller, reference, and shared circuitry; must connect to VIN2 (Pin 7). |
| VIN2 (Pin 7) | LDO2 input | Supplies LDO2; tied to VIN (Pin 6) in standard configurations; supports 2.7–5.5 V range. |
| LDO2 (Pin 8) | LDO2 regulated output | Delivers fixed 2.8 V (per part number suffix); requires ≥2.2 µF X5R/X7R ceramic output capacitor. |
| LDO (Pin 9) | DC/DC LDO output | Provides 1.2 V output in LOWQ mode only; connects to DC/DC output node (VOUT) for seamless handoff. |
| VIN1 (Pin 10) | LDO1 input | Supplies LDO1; supports down to 1.65 V - enables use with partially discharged batteries or intermediate rails. |
| LDO1 (Pin 11) | LDO1 regulated output | Delivers fixed 1.8 V (per part number suffix); requires ≥2.2 µF X5R/X7R ceramic output capacitor. |
| POR (Pin 12) | Open-drain reset output | Asserts low if any output (DC/DC, LDO1, LDO2) falls below 90–99% of nominal; pull-up required externally. |
| CSET (Pin 13) | POR delay timing | 1.25 µA current source charges external capacitor; delay = CSET value in pF (e.g., 10 nF → 10 ms). |
| EN1 (Pin 14) | LDO1 enable | Active-high CMOS input; controls LDO1 independently; floating not allowed. |
| EN (Pin 15) | DC/DC enable | Active-high CMOS input; controls buck converter; tri-states SW when disabled. |
| EN2 (Pin 16) | LDO2 enable | Active-high CMOS input; controls LDO2 independently; floating not allowed. |
Key Features
| Feature | Design Value |
|---|---|
| Triple independent output control | Separate EN, EN1, EN2 pins allow staggered power-up/down sequencing for SoC core, I/O, and peripheral rails. |
| LOWQ ultra-low-noise mode | Disables switching regulator and enables LDO-based DC/DC output path, reducing output noise to 53 µVRMS while drawing only 30 µA. |
| Programmable POR delay | CSET pin accepts external capacitor to set POR assertion delay from microseconds to ~1 second, enabling robust system-level reset coordination. |
| Backup-power-safe POR interface | POR pin has no clamping diodes to supply rails, permitting direct connection to host I/Os powered from backup domains without leakage risk. |
| Thermal and overcurrent protection | Integrated thermal shutdown (160°C trip, 23°C hysteresis) and current limiting (750 mA typical in PWM mode) prevent damage under fault conditions. |
Applications
| Embedded MPU Power Sequencing | Low-Power Wearable Sensor Hub |
|---|---|
Use Scenario: Powering ARM Cortex-A/M series processors with strict voltage ramp requirements and multi-rail dependencies (core, memory, I/O). IC Role / Device Role / Timing Role: Provides three independent, enable-controlled outputs (1.2 V DC/DC, 1.8 V LDO1, 2.8 V LDO2) with programmable POR delay for controlled boot sequence. Use Value: Eliminates need for discrete sequencers or external POR timers; reduces BOM count and layout complexity while ensuring reliable SoC initialization. | Use Scenario: Supplying BLE SoC, MEMS sensors, and display driver in coin-cell–powered fitness tracker with multi-day battery life. IC Role / Device Role / Timing Role: Delivers ultra-low-IQ operation (30 µA in LOWQ mode) during sleep, then switches to 600 mA PWM mode during active sensing/transmission bursts. Use Value: Extends battery runtime by >3× versus conventional PMICs; 53 µVRMS noise prevents RF desense during BLE receive windows. |
| Portable RF Front-End Bias | Industrial Backup Power Management |
Use Scenario: Generating clean, low-noise bias rails for GaAs pHEMT amplifiers and RF ADC/DAC in handheld test equipment. IC Role / Device Role / Timing Role: Uses LOWQ mode to deliver 1.2 V DC/DC output with 53 µVRMS noise, while LDO1 (1.8 V) and LDO2 (2.8 V) power analog front-end stages. Use Value: Avoids PFM-mode ripple that would degrade SNR in RF receivers; eliminates need for post-regulation LC filtering. | Use Scenario: Managing primary and backup power domains in smart meter or PLC controller with supercapacitor backup. IC Role / Device Role / Timing Role: POR output remains valid even when main VIN is removed, as it can be pulled up to backup rail; CSET-programmed delay ensures clean reset after switchover. Use Value: Enables seamless failover without system lockup; eliminates external supervisor IC and associated passive components. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIC2810-4GSYML-TR | Same package and architecture; LDO2 output is 3.3 V instead of 2.8 V. | Suitable where higher LDO2 voltage is needed for 3.3 V I/O or interface logic. | Select when system requires 3.3 V LDO2 rail instead of 2.8 V; otherwise pin- and functionally identical. |
| TPS650703RSLR | TI device with 3 buck + 2 LDO outputs; no LOWQ mode; higher IQ (80 µA typical); different pinout and control scheme. | Preferred for designs needing >3 buck outputs or TI ecosystem integration; unsuitable for ultra-low-noise RF bias. | Choose for higher integration density or TI design continuity; avoid if 53 µVRMS noise or sub-35 µA IQ is mandatory. |
Compared with MIC2810-4GMYML-TR, the -4GSYML-TR offers identical functionality with a 3.3 V LDO2 output for broader I/O compatibility, while the TPS650703RSLR provides more buck channels but lacks LOWQ's ultra-low-noise capability and consumes more quiescent current - making it less suitable for battery-critical or RF-sensitive applications.
Availability
MIC2810-4GMYML-TR is available at Aetrix Electronics and suitable for embedded MPU power sequencing, low-power wearable sensor hubs, and portable RF front-end bias applications requiring stable component supply, long-term lifecycle support, and guaranteed Pb-free industrial-grade qualification (–40°C to +125°C).
Supply support for MIC2810-4GMYML-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, FPGAs, and power management ICs, serving automotive, industrial, consumer, and communications markets with vertically integrated silicon and software solutions.
The MIC2810 product line delivers highly integrated, low-noise, multi-rail power management ICs optimized for space-constrained, battery-powered embedded systems requiring precise sequencing, ultra-low IQ, and RF-clean operation.
FAQ
What output voltages does the MIC2810-4GMYML-TR provide?
The MIC2810-4GMYML-TR provides three fixed output voltages: 1.2 V from the DC/DC converter, 1.8 V from LDO1, and 2.8 V from LDO2. These values are encoded in the part number suffix "4GM" per Microchip's Product Identification System and are non-adjustable. Each output is independently enabled via dedicated EN pins, supporting flexible power sequencing in complex SoC systems.
How does the LOWQ mode affect the MIC2810-4GMYML-TR's DC/DC output behavior?
In LOWQ mode (LOWQ pin pulled low), the MIC2810-4GMYML-TR disables its 2 MHz PWM DC/DC converter and routes the 1.2 V output through an internal LDO path, reducing total quiescent current to 30 µA and output noise to 53 µVRMS. This mode limits DC/DC output current to 60 mA and places LDO1/LDO2 in low-load mode (<50 mA). Full 600 mA PWM operation resumes when LOWQ is pulled high.
Can the MIC2810-4GMYML-TR be used with a 1.65 V input for LDO1?
Yes, the MIC2810-4GMYML-TR supports VIN1 (LDO1 input) down to 1.65 V, enabling operation from partially discharged single-cell Li-ion or NiMH batteries. LDO1 maintains regulation to its 1.8 V output as long as VIN1 ≥ (VOUT + dropout), with typical dropout of 70 mV at 150 mA. This feature is unique to LDO1 - VIN and VIN2 require minimum 2.7 V.
What is the purpose of the CSET pin on the MIC2810-4GMYML-TR?
The CSET pin on the MIC2810-4GMYML-TR sources a precise 1.25 µA current to charge an external capacitor to 1.25 V, setting the POR output assertion delay. The delay in microseconds equals the capacitor value in picofarads (e.g., 10 nF = 10,000 pF → 10 ms delay). This enables customizable power-up sequencing across multiple voltage rails without external timers.
Does the MIC2810-4GMYML-TR support independent enable control for all three outputs?
Yes, the MIC2810-4GMYML-TR provides fully independent enable control: EN (Pin 15) for the DC/DC converter, EN1 (Pin 14) for LDO1, and EN2 (Pin 16) for LDO2. All are active-high CMOS inputs requiring ≥1.0 V for logic high. When disabled, each regulator shuts down completely - e.g., EN = low places the SW node in high-impedance state, eliminating shoot-through risk.
MIC2810-4GMYML-TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 16-VQFN Exposed Pad, 16-MLF®
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) (1), Linear (LDO) (2)
- Number of Outputs:
- 3
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- 1.2V, 600mA
- Voltage/Current - Output 2:
- 1.8V, 300mA
- Voltage/Current - Output 3:
- 2.8V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-MLF® (4x4)
MIC2810-4GMYML-TR FAQ
1.How can I place an order for MIC2810-4GMYML-TR through Aetrix?
Please submit a Request for Quotation (RFQ) for MIC2810-4GMYML-TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIC2810-4GMYML-TR reliable?
The price and inventory of MIC2810-4GMYML-TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIC2810-4GMYML-TR is usually 5 days.
3.What payment methods are accepted for MIC2810-4GMYML-TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIC2810-4GMYML-TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIC2810-4GMYML-TR?
MIC2810-4GMYML-TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIC2810-4GMYML-TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIC2810-4GMYML-TR?
For technical support, including MIC2810-4GMYML-TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIC2810-4GMYML-TR requirements.
6.How does Aetrix verify that MIC2810-4GMYML-TR is sourced from the original manufacturer or authorized distributors?
All MIC2810-4GMYML-TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIC2810-4GMYML-TR meets industry standards.
7.What is the process for return or replacement of MIC2810-4GMYML-TR?
All MIC2810-4GMYML-TR units undergo pre-shipment inspection (PSI). If there is an issue with MIC2810-4GMYML-TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIC2810-4GMYML-TR part is unused and in its original packaging.
Return procedure for MIC2810-4GMYML-TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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