Microchip Technology MIC2810-CGJYML-TR
- Part No.:
- MIC2810-CGJYML-TR
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-VQFN Exposed Pad, 16-MLF®
- Datasheet:
-
MIC2810-CGJYML-TR.pdf
- Description:
- IC REG TRPL BUCK/LNR 2MHZ 16MLF
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
MIC2810-CGJYML-TR from Microchip Technology is a digital power management IC integrating a 2 MHz, 600 mA DC/DC buck converter and two independent 300 mA LDOs (1.2 V / 1.8 V / 2.5 V outputs), with LOWQ ultra-low-noise light-load mode, integrated power-on reset (POR), and 16-pin 3 mm × 3 mm QFN packaging. It delivers stable multi-rail power for embedded MPU subsystems requiring low quiescent current and RF-clean operation.
For engineers reviewing the MIC2810-CGJYML-TR datasheet, MIC2810-CGJYML-TR pinout, MIC2810-CGJYML-TR application, or MIC2810-CGJYML-TR equivalent, this page provides verified functional identity, confirmed pin roles, exact output voltage configuration (1.2 V DC/DC, 1.8 V LDO1, 2.5 V LDO2), LOWQ-mode noise (53 µVRMS), thermal shutdown protection, and validated alternative options for multi-rail portable power designs.
Technical Context
The MIC2810-CGJYML-TR implements a dual-domain architecture: a high-efficiency 2 MHz PWM DC/DC converter (up to 600 mA) co-integrated with two low-dropout linear regulators (LDO1/LDO2, each up to 300 mA), all sharing independent enable control and a unified LOWQ mode that disables switching and reduces total IQ to ≤30 µA. Its POR circuit performs logic-OR monitoring across all three outputs with programmable delay via CSET capacitor.
Pin separation enforces signal integrity: SGND handles bias/reference paths while PGND carries high-current PWM return; BIAS supplies internal circuitry through a 6 Ω resistor; SW connects directly to external inductor; and LDO pin serves as shared output node for DC/DC in LOWQ mode. The device supports sequencing-aware startup via CSET-controlled POR delay and enables leakage-free backup-power interfacing via open-drain POR with no clamping diodes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | VIN/VIN2: 2.7–5.5 V; VIN1: 1.65–5.5 V - supports wide-input battery and rail-sourced systems with asymmetric LDO input capability. |
| DC/DC Output Current | 600 mA (PWM mode); 60 mA (LOWQ mode) - enables full-power operation or ultra-low-noise standby without external reconfiguration. |
| LDO Output Current | 300 mA per LDO (LDO1/LDO2) - sufficient for core logic, memory, and I/O rails in compact embedded systems. |
| LOWQ Mode IQ | ≤30 µA total - extends battery life in always-on wearable and sensor nodes while maintaining regulated outputs. |
| DC/DC Output Noise | 53 µVRMS (10 Hz–100 kHz, LOWQ mode) - avoids interference with sensitive RF receivers and precision analog circuits. |
| Thermal Protection | 160 °C shutdown with 23 °C hysteresis - prevents permanent damage during sustained overload or poor PCB thermal design. |
| Package | 16-pin 3 mm × 3 mm QFN, 0.85 mm height - enables high-density layout with exposed thermal pad for efficient heat dissipation. |
Pinout & Package
Package: 16-lead 3 mm × 3 mm QFN (ML suffix), Pb-free, industrial temperature grade (–40°C to +125°C), with exposed thermal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (LOWQ) | Mode Control Input | Active-low logic input selecting between 2 MHz PWM mode (HIGH) and ultra-low-noise linear mode (LOW); must not float. |
| 2 (BIAS) | Bias Supply Terminal | Powers internal reference/control circuitry via internal 6 Ω resistor; requires 0.1 µF bypass to SGND. |
| 3 (SGND) | Signal Ground | Return path for low-current bias, reference, and logic circuits; must be routed separately from PGND. |
| 4 (PGND) | Power Ground | High-current return path for DC/DC switch node; requires low-inductance connection to thermal pad. |
| 5 (SW) | Switch Node Output | Drives external inductor in PWM mode; high dv/dt node requiring careful routing away from sensitive traces. |
| 6 (VIN) | Main Input Supply | Primary input for DC/DC controller, LDO1, LDO2, and internal circuitry; must connect to Pin 7 (VIN2). |
| 7 (VIN2) | LDO2 Input Supply | Input for LDO2; electrically tied to VIN (Pin 6) per datasheet requirement. |
| 8 (LDO2) | LDO2 Regulated Output | Fixed 2.5 V output (per CGJ variant); requires ≥2.2 µF ceramic capacitor for stability. |
| 9 (LDO) | DC/DC Output Node (LOWQ) | Shared output terminal used only in LOWQ mode; connects to DC/DC output when switching disabled. |
| 10 (VIN1) | LDO1 Input Supply | Input for LDO1; supports down to 1.65 V, enabling use with partially discharged batteries or low-VIN sources. |
| 11 (LDO1) | LDO1 Regulated Output | Fixed 1.8 V output (per CGJ variant); requires ≥2.2 µF ceramic capacitor for stability. |
| 12 (POR) | Open-Drain Power-On Reset | Asserts low if any output (DC/DC, LDO1, LDO2) falls out of regulation; no clamping diodes enable backup-domain interfacing. |
| 13 (CSET) | POR Delay Timing Input | Current source (1.25 µA typ.) charging external capacitor to set POR assertion delay; delay = CSET (pF) in µs. |
| 14 (EN1) | LDO1 Enable Input | Active-high CMOS input controlling LDO1; 1.0 V min VIH ensures robust logic-level compatibility. |
| 15 (EN) | DC/DC Enable Input | Active-high CMOS input controlling DC/DC converter; tri-states SW node when disabled. |
| 16 (EN2) | LDO2 Enable Input | Active-high CMOS input controlling LDO2; independent sequencing control enables staggered power-up. |
Key Features
| Feature | Design Value |
|---|---|
| Triple-output power architecture | Single-chip integration of 2 MHz DC/DC (1.2 V) + dual LDOs (1.8 V, 2.5 V) eliminates discrete PMIC complexity and board space. |
| LOWQ ultra-low-noise mode | Reduces total IQ to ≤30 µA while delivering 53 µVRMS output noise - critical for RF, audio, and precision analog subsystems. |
| Independent enable control | Three separate EN pins (EN, EN1, EN2) allow precise sequencing of DC/DC and both LDOs for SoC boot requirements. |
| Backup-power-safe POR | Open-drain POR with no supply-rail clamping diodes enables direct connection to backup domains without parasitic leakage. |
| Thermal and current protection | Integrated thermal shutdown (160 °C) and current limiting (600 mA DC/DC, 300 mA LDOs) ensure robust operation under fault conditions. |
Applications
| Embedded MPU Power | Wearable Sensor Hub |
|---|---|
Use Scenario: Powering ARM Cortex-A/M series processors with multiple voltage rails (core, I/O, memory) in space-constrained edge devices. IC Role / Device Role / Timing Role: Primary multi-rail power source providing sequenced 1.2 V (DC/DC), 1.8 V (LDO1), and 2.5 V (LDO2) with independent enable control. Use Value: Eliminates need for three discrete regulators; LOWQ mode extends runtime during idle periods without compromising RF performance. |
Use Scenario: Battery-powered health monitors requiring continuous sensor sampling, BLE radio operation, and low-power sleep states. IC Role / Device Role / Timing Role: Central power manager delivering clean 1.2 V for MCU, 1.8 V for sensors, and 2.5 V for BLE transceiver with POR coordination. Use Value: 53 µVRMS noise in LOWQ mode prevents BLE packet loss; <30 µA quiescent current enables multi-week battery life. |
| Low-Power RF Transceiver | Backup Power System |
Use Scenario: Powering sub-GHz or 2.4 GHz RF ICs (e.g., Si4463, nRF52840) where switching noise can degrade sensitivity and EVM. IC Role / Device Role / Timing Role: Low-noise power source using LOWQ mode during receive intervals and PWM mode during transmit bursts. Use Value: Switches seamlessly between 53 µVRMS (LOWQ) and >90% efficiency (PWM), avoiding PFM-induced spurs that degrade RF metrics. |
Use Scenario: Real-time clock (RTC) and SRAM retention during main power failure in industrial controllers or smart meters. IC Role / Device Role / Timing Role: Dual-role regulator: primary power source during normal operation; leakage-free POR signaling to host MCU during backup mode. Use Value: POR pin operates without parasitic current draw even when main VIN is removed - enabling reliable backup-domain wake-up detection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIC2810-4GSYML-TR | Output voltages: 1.2 V / 1.8 V / 3.3 V (vs. 1.2 V / 1.8 V / 2.5 V); otherwise identical pinout, features, and specs. | Targets systems requiring 3.3 V I/O rail instead of 2.5 V; not suitable where 2.5 V LDO2 is mandatory. | Select when 3.3 V LDO2 is needed; verify compatibility with downstream 2.5 V loads. |
| MIC2810-FGSYML-TR | Output voltages: 1.5 V / 1.8 V / 3.3 V; higher DC/DC output enables different core voltage scaling. | Suitable for 1.5 V processor cores or mixed-voltage FPGA I/O banks; incompatible with 1.2 V DC/DC-dependent loads. | Choose for 1.5 V core rail applications; confirm LDO1/LDO2 voltage alignment with system requirements. |
Compared with MIC2810-CGJYML-TR, the 4GSYML-TR offers identical functionality but targets 3.3 V LDO2 loads, while FGSYML-TR shifts DC/DC output to 1.5 V for higher-core-voltage processors - both require voltage-specific PCB validation and cannot substitute without schematic review.
Availability
MIC2810-CGJYML-TR is available at Aetrix Electronics and suitable for embedded MPU power, wearable sensor hubs, low-power RF transceivers, and backup power systems requiring stable component supply, long-term lifecycle support, and industrial-grade temperature performance.
Supply support for MIC2810-CGJYML-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and power management ICs, serving automotive, industrial, communications, and consumer markets with vertically integrated silicon and software solutions.
The MIC2810 product line delivers highly integrated, sequenced multi-rail power management for space- and power-constrained embedded systems, emphasizing ultra-low-noise operation, backup-power resilience, and simplified design-in for portable and industrial applications.
FAQ
What output voltages does the MIC2810-CGJYML-TR provide?
The MIC2810-CGJYML-TR provides fixed output voltages of 1.2 V from its DC/DC converter, 1.8 V from LDO1, and 2.5 V from LDO2 - as defined by the "CGJ" output code in the part number and confirmed in Microchip's Product Identification System. These values are factory-trimmed and non-adjustable; no external feedback resistors are required or supported.
How does LOWQ mode affect the MIC2810-CGJYML-TR's output capability and noise performance?
In LOWQ mode (LOWQ pin pulled low), the MIC2810-CGJYML-TR disables its PWM switching stage and regulates the DC/DC output via the LDO pin, reducing total quiescent current to ≤30 µA and output noise to 53 µVRMS (10 Hz–100 kHz). However, DC/DC output current is limited to 60 mA, and LDO1/LDO2 load current is capped at <50 mA - making LOWQ ideal for ultra-low-power standby, not active operation.
Can the MIC2810-CGJYML-TR support independent power sequencing for its three outputs?
Yes - the MIC2810-CGJYML-TR supports full independent sequencing via three dedicated enable inputs: EN (DC/DC), EN1 (LDO1), and EN2 (LDO2), all active-high CMOS-compatible. Combined with programmable POR delay (via CSET capacitor), it enables precise turn-on order, hold-off timing, and fault detection across all rails - essential for complex SoCs and FPGAs.
What is the purpose of the POR pin on the MIC2810-CGJYML-TR, and how is it implemented?
The POR pin on the MIC2810-CGJYML-TR is an open-drain output that asserts low whenever any of the three regulated outputs (DC/DC, LDO1, or LDO2) falls outside its regulation window. It features no clamping diodes to VIN or VOUT, allowing safe connection to backup power domains. A pull-up resistor is required, and delay time is set by a capacitor on the CSET pin (1 pF = 1 µs).
What package type and thermal characteristics apply to the MIC2810-CGJYML-TR?
The MIC2810-CGJYML-TR uses a 16-pin 3 mm × 3 mm QFN package (ML suffix) with exposed thermal pad, rated for –40°C to +125°C operation. Its junction-to-air thermal resistance (θJA) is 56 °C/W. For reliable operation at full load, the PCB must include adequate copper area under the thermal pad and proper vias to inner ground planes to maintain TJ ≤ 125°C.
MIC2810-CGJYML-TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 16-VQFN Exposed Pad, 16-MLF®
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) (1), Linear (LDO) (2)
- Number of Outputs:
- 3
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- 1.2V, 600mA
- Voltage/Current - Output 2:
- 1.8V, 300mA
- Voltage/Current - Output 3:
- 2.5V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-MLF® (4x4)
MIC2810-CGJYML-TR FAQ
1.How can I place an order for MIC2810-CGJYML-TR through Aetrix?
Please submit a Request for Quotation (RFQ) for MIC2810-CGJYML-TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIC2810-CGJYML-TR reliable?
The price and inventory of MIC2810-CGJYML-TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIC2810-CGJYML-TR is usually 5 days.
3.What payment methods are accepted for MIC2810-CGJYML-TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIC2810-CGJYML-TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIC2810-CGJYML-TR?
MIC2810-CGJYML-TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIC2810-CGJYML-TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIC2810-CGJYML-TR?
For technical support, including MIC2810-CGJYML-TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIC2810-CGJYML-TR requirements.
6.How does Aetrix verify that MIC2810-CGJYML-TR is sourced from the original manufacturer or authorized distributors?
All MIC2810-CGJYML-TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIC2810-CGJYML-TR meets industry standards.
7.What is the process for return or replacement of MIC2810-CGJYML-TR?
All MIC2810-CGJYML-TR units undergo pre-shipment inspection (PSI). If there is an issue with MIC2810-CGJYML-TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIC2810-CGJYML-TR part is unused and in its original packaging.
Return procedure for MIC2810-CGJYML-TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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