Microchip Technology MIC5320-PGYMT-TR
- Part No.:
- MIC5320-PGYMT-TR
- Manufacturer:
- Microchip Technology
- Package:
- 6-UFDFN Exposed Pad, 6-TMLF®
- Datasheet:
-
MIC5320-PGYMT-TR.pdf
- Description:
- IC REG LINEAR 1.8V/3V 6TMLF
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
MIC5320-PGYMT-TR from Micrel is a dual ultra-low-dropout (ULDO™) linear regulator delivering two independent 150mA outputs at fixed 3.0V and 1.8V, designed for space-constrained portable electronics. It operates from 2.3V to 5.5V input, achieves 35mV dropout at full load, and stabilizes with only 1µF ceramic output capacitors in a 1.6mm × 1.6mm Thin MLF® package - enabling compact power management in mobile phone camera modules and imaging sensors.
For engineers reviewing the MIC5320-PGYMT-TR datasheet, MIC5320-PGYMT-TR pinout, MIC5320-PGYMT-TR application, or MIC5320-PGYMT-TR equivalent, key selection criteria include dual-output voltage pairing, µCap stability with minimal external capacitance, thermal performance in ultra-small footprint, and independent active-high enable control per LDO channel.
Technical Context
The MIC5320-PGYMT-TR integrates two independent CMOS-based ULDO regulators sharing a common VIN and GND, each with dedicated EN1/EN2 pins enabling asynchronous on/off control. Its µCap architecture eliminates need for large bulk capacitance by leveraging high-bandwidth error amplifiers and optimized internal compensation.
Each LDO features 2% output voltage accuracy over –40°C to +125°C, 65dB PSRR at 1kHz, and fast 30µs turn-on time. Thermal shutdown and current-limit protection (300–950mA) are implemented per channel, with ground current as low as 85µA per enabled output.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltages | 3.0V (LDO1) and 1.8V (LDO2), fixed and non-adjustable - supports dual-rail SoC or image sensor biasing without external feedback networks. |
| Max Output Current | 150mA per channel - sufficient for powering digital camera ISPs, CMOS image sensors, or baseband processors in ultra-thin form factors. |
| Dropout Voltage | 35mV @ 150mA - enables regulation from 3.035V input for 3.0V rail and 1.835V for 1.8V rail, maximizing battery runtime in Li-ion-powered devices. |
| Input Voltage Range | 2.3V to 5.5V - compatible with single-cell Li-ion (2.7–4.2V), USB 5V, or boosted 3.3V supplies across portable platforms. |
| Output Capacitor | 1µF ceramic minimum per output - reduces PCB area and BOM cost versus traditional LDOs requiring ≥10µF tantalum or aluminum electrolytic. |
| Quiescent Current | 85µA per enabled output - ensures low standby power in always-on camera modules or GPS receivers during sleep mode. |
| Enable Logic | Active-high EN1/EN2 with 1.1V logic-high threshold - interfaces directly with 1.8V/3.3V GPIOs without level-shifting, and requires no pull-up resistors. |
Pinout & Package
Package: 6-pin 1.6mm × 1.6mm leadless Thin MLF® (MT) with exposed thermal pad (EPAD) internally connected to GND - delivers θJA = 100°C/W for high-power-density thermal management in thin-profile assemblies.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (VIN) | Supply Input | Common input for both LDOs; must be bypassed with ≥1µF ceramic capacitor to GND for stability and noise rejection. |
| 2 (GND) | Ground Reference | Power and signal return; connects to EPAD for optimal thermal conduction and low-noise grounding. |
| 3 (EN2) | Enable Input (LDO2) | Active-high control for 1.8V output; logic low disables LDO2 and reduces ground current to ≤2µA. |
| 4 (EN1) | Enable Input (LDO1) | Active-high control for 3.0V output; independent of EN2, enabling flexible power sequencing in multi-rail systems. |
| 5 (VOUT2) | LDO2 Output | 1.8V regulated output capable of sourcing 150mA; requires ≥1µF ceramic capacitor to GND for stability. |
| 6 (VOUT1) | LDO1 Output | 3.0V regulated output capable of sourcing 150mA; decoupling capacitor placement must minimize trace inductance for transient response. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent ULDOs | Enables simultaneous regulation of core (3.0V) and I/O (1.8V) rails in camera modules without cross-coupling or shared enable constraints. |
| µCap stability | Eliminates need for large output capacitors - reduces total solution size by >50% vs. conventional LDOs requiring ≥10µF, critical for <10mm² PCB real estate. |
| Ultra-low dropout | 35mV @ 150mA allows operation down to 1.835V input for 1.8V rail, extending usable battery voltage range in single-cell Li-ion applications. |
| Fast transient response | 30µs turn-on time and high PSRR (>65dB @ 1kHz) maintain stable output during rapid load steps typical in burst-mode image capture. |
| Thermal protection | Integrated thermal shutdown activates at ~150°C junction temperature - prevents damage during sustained overload or poor heatsinking in sealed enclosures. |
Applications
| Mobile Camera Module Power | Dual-Rail Sensor Biasing |
|---|---|
Use Scenario: Powering CMOS image sensor and companion ISP in smartphone front/rear cameras with strict height and thermal constraints. IC Role / Device Role / Timing Role: Dual-output LDO providing isolated 3.0V analog and 1.8V digital rails with independent enable control for power sequencing. Use Value: Eliminates need for discrete regulators or DC-DC + LDO combos, reducing component count and board area while maintaining <2% output accuracy across temperature. | Use Scenario: Supplying separate voltage domains for high-speed ADC interface (3.0V) and low-voltage logic core (1.8V) in portable medical imaging devices. IC Role / Device Role / Timing Role: Precision dual-LDO delivering tightly regulated, low-noise supplies with fast transient recovery during dynamic sampling cycles. Use Value: 90µVRMS output noise and 65dB PSRR suppress supply-induced artifacts in 12-bit+ image data acquisition. |
| GPS Receiver Core Power | Ultra-Thin PMP Audio Codec Supply |
Use Scenario: Providing clean, sequenced power to GPS baseband processor and RF front-end in wearable navigation units. IC Role / Device Role / Timing Role: Low-quiescent-current dual LDO enabling deep-sleep modes (≤2µA shutdown) while supporting rapid wake-up via independent EN pins. Use Value: 85µA quiescent current per enabled output extends battery life in intermittent-use GPS tracking applications beyond 72 hours. | Use Scenario: Powering stereo audio codec and flash memory controller in sub-10mm-thick portable media players. IC Role / Device Role / Timing Role: Compact dual-LDO replacing larger SOT-23-6 solutions, fitting within narrow edge zones of rigid-flex PCBs. Use Value: 1.6mm × 1.6mm footprint occupies <30% area of SOT-23-6, freeing space for battery expansion or antenna tuning elements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6223D301MR-G | Single 3.0V output (not dual); 200mA rating; 150mV dropout @ 200mA; same 1.6×1.6mm USP-6B package. | Cannot replace MIC5320-PGYMT-TR's dual-rail capability - requires second regulator for 1.8V rail. | Select when only 3.0V rail is needed and higher current margin is required; not suitable for direct dual-output substitution. |
| Ricoh RP512F301D-TR-F | Dual-output (3.0V/1.8V); 200mA per channel; 120mV dropout @ 200mA; 2.0×2.0mm DFN-8 package. | Larger footprint (+56% area) and higher dropout reduce efficiency and board density vs. MIC5320-PGYMT-TR. | Consider for designs needing higher current headroom where PCB area is less constrained; verify thermal performance at 150mA in DFN-8 layout. |
Compared with XC6223D301MR-G and RP512F301D-TR-F, the MIC5320-PGYMT-TR uniquely combines dual 150mA outputs, 35mV ultra-low dropout, and 1.6mm × 1.6mm footprint - making it optimal for space-limited, battery-sensitive dual-rail applications where efficiency and miniaturization are prioritized over raw current headroom.
Availability
MIC5320-PGYMT-TR is available at Aetrix Electronics and suitable for mobile camera modules, GPS receivers, and portable media players requiring stable component supply with guaranteed long-term availability and RoHS-compliant packaging.
Supply support for MIC5320-PGYMT-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Micrel Inc. was a U.S.-based semiconductor company specializing in analog, power management, and timing solutions before its acquisition by Microchip Technology in 2015.
The MIC5320 product line was engineered for ultra-thin portable electronics, emphasizing minimal footprint, µCap compatibility, and dual-output flexibility to simplify power architecture in space-constrained imaging and communication devices.
FAQ
What are the exact output voltages of the MIC5320-PGYMT-TR?
The MIC5320-PGYMT-TR provides fixed 3.0V on VOUT1 (Pin 6) and 1.8V on VOUT2 (Pin 5). These values are trimmed at wafer test and guaranteed within ±2% at 25°C and ±3% over –40°C to +125°C operating range, as specified in the official Micrel datasheet revision M9999-021111-H.
Can the MIC5320-PGYMT-TR operate with zero load on either output?
Yes, the MIC5320-PGYMT-TR remains stable and in regulation with no load on either output - a feature explicitly confirmed in the Applications Information section of the datasheet. This supports use cases like CMOS RAM keep-alive circuits where one rail may be idle while the other is active.
What is the recommended input capacitor for the MIC5320-PGYMT-TR?
A minimum 1µF X7R ceramic capacitor is required from VIN (Pin 1) to GND (Pin 2), placed as close as possible to the device. The datasheet specifies low-ESR ceramics for optimal performance and warns against high-ESR types (e.g., Y5V) that may cause oscillation - the MIC5320-PGYMT-TR's stability is validated only with proper 1µF input bypassing.
Does the MIC5320-PGYMT-TR support independent power sequencing?
Yes, the MIC5320-PGYMT-TR features independent active-high enable pins: EN1 (Pin 4) controls the 3.0V output and EN2 (Pin 3) controls the 1.8V output. Each pin has a 1.1V logic-high threshold and can be driven separately by microcontroller GPIOs, enabling precise sequencing such as powering the 3.0V analog rail before enabling the 1.8V digital domain.
What thermal resistance does the MIC5320-PGYMT-TR exhibit in its Thin MLF® package?
The MIC5320-PGYMT-TR in the 6-pin 1.6mm × 1.6mm Thin MLF® (MT) package has a junction-to-ambient thermal resistance (θJA) of 100°C/W under standard minimum footprint conditions, as documented in the Absolute Maximum Ratings table. This value assumes proper PCB copper pour connected to the EPAD for heat dissipation.
MIC5320-PGYMT-TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 6-UFDFN Exposed Pad, 6-TMLF®
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 2
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.8V, 3V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.1V @ 150mA, 0.1V @ 150mA
- Current - Output:
- 150mA, 150mA
- Current - Quiescent (Iq):
- 120 µA
- Current - Supply (Max):
- 190 µA
- PSRR:
- 65dB ~ 45dB (1kHz ~ 20kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TMLF® (1.6x1.6)
MIC5320-PGYMT-TR FAQ
1.How can I place an order for MIC5320-PGYMT-TR through Aetrix?
Please submit a Request for Quotation (RFQ) for MIC5320-PGYMT-TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIC5320-PGYMT-TR reliable?
The price and inventory of MIC5320-PGYMT-TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIC5320-PGYMT-TR is usually 5 days.
3.What payment methods are accepted for MIC5320-PGYMT-TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIC5320-PGYMT-TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIC5320-PGYMT-TR?
MIC5320-PGYMT-TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIC5320-PGYMT-TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIC5320-PGYMT-TR?
For technical support, including MIC5320-PGYMT-TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIC5320-PGYMT-TR requirements.
6.How does Aetrix verify that MIC5320-PGYMT-TR is sourced from the original manufacturer or authorized distributors?
All MIC5320-PGYMT-TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIC5320-PGYMT-TR meets industry standards.
7.What is the process for return or replacement of MIC5320-PGYMT-TR?
All MIC5320-PGYMT-TR units undergo pre-shipment inspection (PSI). If there is an issue with MIC5320-PGYMT-TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIC5320-PGYMT-TR part is unused and in its original packaging.
Return procedure for MIC5320-PGYMT-TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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