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Microchip Technology MIC5373-SJGYMT-TR
- Part No.:
- MIC5373-SJGYMT-TR
- Manufacturer:
- Microchip Technology
- Package:
- 16-UFQFN Exposed Pad, 16-MLF®
- Datasheet:
-
MIC5373-SJGYMT-TR.pdf
- Description:
- IC REG LIN 1.8V/2.5V/3.3V 16MLF
- Quantity:
- Payment:
- Shipping:
Inventory:3,587
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Product details
Overview
MIC5373-SJGYMT-TR from Micrel is a triple-output, active-high-enable LDO regulator IC delivering 200mA per channel at fixed outputs of 3.3V, 2.5V, and 1.8V. It features independent enable pins, high PSRR (55dB at 1kHz), low noise (200µVRMS), and integrated power-on-reset with adjustable delay-designed for powering RF-sensitive subsystems in mobile application processors.
For engineers reviewing the MIC5373-SJGYMT-TR datasheet, MIC5373-SJGYMT-TR pinout, MIC5373-SJGYMT-TR application, or MIC5373-SJGYMT-TR equivalent, key selection criteria include output voltage set, enable polarity, POR monitoring flexibility, thermal performance in 2.5mm × 2.5mm Thin MLF, and stability with 1µF ceramic capacitors.
Technical Context
The MIC5373-SJGYMT-TR integrates three independent CMOS-based LDOs sharing a common BIAS rail but with separate input (INLDO1/2, INLDO3) and enable (EN1/EN2/EN3) paths. Each LDO operates from 1.7V to 5.5V input and maintains ±2% output accuracy across −40°C to +125°C junction temperature.
Its POR circuit monitors voltage via POR_IN against a 0.9V internal reference, uses a 1.25µA current source to charge an external capacitor on DLY, and asserts an open-drain POR output after reaching 1.25V-enabling user-defined reset timing and manual reset via MR.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output voltages | 3.3V / 2.5V / 1.8V - fixed, simultaneous triple-rail supply for AP core, I/O, and memory subsystems |
| Max output current | 200mA per LDO - supports moderate-power RF blocks (GPS/WiFi/Bluetooth) without external boost |
| Dropout voltage | 170mV at 150mA - enables operation with tight VIN–VOUT margins (e.g., 3.47V input for 3.3V rail) |
| PSRR | 55dB at 1kHz - suppresses switching noise from PMIC or DC-DC converters feeding LDO inputs |
| Output noise | 200µVRMS (10Hz–100kHz) - meets low-noise requirements for RF receiver analog front-ends |
| Enable polarity | Active-high (EN1/EN2/EN3) - simplifies direct GPIO control from application processor without inverters |
| Package | 16-pin 2.5mm × 2.5mm Thin MLF - ultra-compact footprint for space-constrained mobile PCBs |
Pinout & Package
Package: 16-pin 2.5mm × 2.5mm Thin MLF (exposed EPAD grounded). Pinout validated per Micrel MIC5373 datasheet Rev. September 2012, pages 3–4.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OUT1) | LDO1 regulated output | 3.3V rail; requires ≥1µF ceramic capacitor placed adjacent to pin |
| 2 (INLDO1/2) | Shared input for LDO1 & LDO2 | Accepts 1.7–5.5V; decouple with 1µF ceramic near pin and GND |
| 3 (OUT2) | LDO2 regulated output | 2.5V rail; same capacitor requirement as OUT1 |
| 4 (BIAS) | Internal bias supply | Must be decoupled to GND with 0.1µF ceramic; powers reference/control circuitry |
| 5 (POR_IN) | POR voltage monitor input | Compares external voltage to 0.9V reference; supports resistor divider for custom threshold |
| 6 (POR) | Open-drain POR output | Asserted high after DLY capacitor charges to 1.25V; requires external pull-up (10kΩ–100kΩ) |
| 7 (DLY) | POR delay timing node | 1.25µA current source charges external capacitor; delay = CDLY × 1s/µF |
| 8 (MR) | Manual reset input | Logic-high (>1.2V) forces POR low; logic-low (<0.2V) restarts DLY timing |
| 9,10 (NC) | No connect | Not bonded; leave unconnected and unrouted |
| 11 (INLDO3) | Input for LDO3 | Independent 1.7–5.5V supply path for 1.8V rail |
| 12 (OUT3) | LDO3 regulated output | 1.8V rail; supports digital core/memory I/O domains |
| 13 (GND) | Power and signal ground | Common return for all LDOs, BIAS, POR, and EPAD; low-inductance connection required |
| 14 (EN3) | LDO3 enable (active-high) | High = ON; low = OFF; must not float - tie to GND or controlled GPIO |
| 15 (EN2) | LDO2 enable (active-high) | Same behavior as EN3; enables independent power sequencing |
| 16 (EN1) | LDO1 enable (active-high) | Enables 3.3V rail independently; supports dynamic power gating |
| EPAD | Exposed thermal pad | Must be soldered to solid GND plane for thermal dissipation (θJA = 100°C/W) |
Key Features
| Feature | Design Value |
|---|---|
| Triple 200mA LDOs with independent enables | Enables per-rail power control and sequencing for multi-voltage SoC subsystems |
| Integrated POR with user-adjustable delay | Eliminates need for external supervisor IC; delay set by single capacitor (e.g., 1µF = 1s) |
| High PSRR (55dB @ 1kHz) and low noise (200µVRMS) | Preserves signal integrity in GPS/WiFi RF chains powered directly from LDO outputs |
| Stable with 1µF ceramic output capacitors | Reduces BOM count and board area vs. legacy LDOs requiring ≥10µF tantalum |
| Thermal shutdown and current limit protection | Self-protects during overload or ambient temperature excursions up to +125°C junction |
Applications
| Mobile Application Processors | GPS/WiFi/Bluetooth RF Modules |
|---|---|
Use Scenario: Powering core, I/O, and memory rails of ARM-based application processors in smartphones and tablets. IC Role / Device Role / Timing Role: Triple-LDO delivers clean, sequenced 3.3V/2.5V/1.8V supplies; EN pins enable dynamic power gating per subsystem. Use Value: Reduces component count versus discrete LDOs while maintaining rail independence and low noise. | Use Scenario: Supplying analog and digital sections of GNSS receivers and 2.4GHz transceivers. IC Role / Device Role / Timing Role: Low-noise 3.3V/2.5V rails power LNA/VCO/ADC; POR ensures reliable RF IC initialization after cold start. Use Value: 200µVRMS noise and 55dB PSRR prevent reciprocal mixing and phase noise degradation. |
| Portable Medical Sensors | Industrial Handheld Terminals |
Use Scenario: Powering precision analog front-ends (AFE) and low-power microcontrollers in battery-operated diagnostic devices. IC Role / Device Role / Timing Role: 1.8V LDO powers MCU core; 2.5V rail supplies ADC reference; POR coordinates system wake-up. Use Value: ±2% output accuracy and −40°C to +125°C operation ensure clinical-grade measurement stability. | Use Scenario: Supporting barcode scanners, RFID readers, and ruggedized displays in warehouse logistics hardware. IC Role / Device Role / Timing Role: Triple-rail supply powers display driver (3.3V), baseband processor (2.5V), and flash memory interface (1.8V). Use Value: Active-high enables simplify integration with existing GPIO-controlled power trees; Thin MLF eases mechanical design. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIC5383-SJGYMT-TR | Identical specs except active-low enable pins (/EN1–/EN3); same package, voltage set, and POR functionality | Requires inverted logic drive (e.g., from open-drain buffer or FPGA with active-low enables) | Select when system control logic natively provides active-low signals or shares enable nets with other /EN devices |
| TSM1033TR | Triple 300mA LDO; 3.3V/2.8V/1.8V outputs; no integrated POR; 20V max input; SO-16 package (4.9mm × 6.0mm) | Larger footprint; lacks voltage-monitoring and reset delay features; higher dropout (300mV @ 250mA) | Choose when higher current per rail is needed and POR is implemented externally or omitted |
Compared with MIC5383-SJGYMT-TR, the MIC5373-SJGYMT-TR offers native GPIO-compatible enable logic; versus TSM1033TR, it trades higher current for smaller size, lower noise, and integrated supervision-critical for compact RF designs.
Availability
MIC5373-SJGYMT-TR is available at Aetrix Electronics and suitable for mobile platforms, GPS receivers, and application co-processors requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for MIC5373-SJGYMT-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Micrel Inc. was a U.S.-based semiconductor company specializing in power management, timing, and analog ICs before its acquisition by Microchip Technology in 2015. Its LDO portfolio emphasized high PSRR and small-footprint solutions for portable electronics.
The MIC5373 family targets mobile and wireless applications needing compact, low-noise, multi-rail power with integrated power-on-reset-designed to replace discrete LDO + supervisor combinations in space-constrained designs.
FAQ
What output voltages does the MIC5373-SJGYMT-TR provide?
The MIC5373-SJGYMT-TR provides three fixed, simultaneous output voltages: 3.3V (OUT1), 2.5V (OUT2), and 1.8V (OUT3). These are factory-set and non-adjustable. The ordering code "SJG" explicitly denotes this voltage combination per Micrel's ordering information table, and all electrical characteristics-including load regulation and dropout-are specified for these exact outputs.
Does the MIC5373-SJGYMT-TR require external components to operate?
Yes, the MIC5373-SJGYMT-TR requires external capacitors: a 0.1µF ceramic capacitor on BIAS-to-GND, 1µF ceramics on each INLDO and OUT pin, and an optional capacitor on DLY-to-GND for POR delay. No resistors are mandatory, though a pull-up on POR and optional divider on POR_IN are used for supervision functions. These values are specified in the datasheet's Application Information section.
How is power-on-reset timing configured on the MIC5373-SJGYMT-TR?
Power-on-reset timing on the MIC5373-SJGYMT-TR is set by an external capacitor connected between the DLY pin and GND. A constant 1.25µA current charges this capacitor; when voltage reaches 1.25V, POR asserts high. Delay time (seconds) = CDLY (in µF) × 1. For example, a 100nF capacitor yields ~100ms delay. This method is confirmed in the Pin Description and Application Information sections of the datasheet.
Can the MIC5373-SJGYMT-TR monitor a voltage other than its own outputs?
Yes, the MIC5373-SJGYMT-TR can monitor any external voltage using the POR_IN pin. The internal 0.9V reference allows direct connection to a target rail (e.g., main PMIC output), or a resistor divider can scale higher voltages (e.g., 5V or 12V) down to ≤0.9V for precise undervoltage detection. This capability is explicitly described in the POR_IN pin function and Application Information sections.
What thermal considerations apply to the MIC5373-SJGYMT-TR in continuous operation?
The MIC5373-SJGYMT-TR has a junction-to-ambient thermal resistance (θJA) of 100°C/W in its 2.5mm × 2.5mm Thin MLF package. At full 150mA load per LDO with typical voltage drops, power dissipation approaches 0.75W, limiting maximum ambient temperature to ~50°C with minimal copper area. Full thermal calculations and layout guidance-including mandatory EPAD grounding-are provided in the datasheet's Thermal Considerations section.
MIC5373-SJGYMT-TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 16-UFQFN Exposed Pad, 16-MLF®
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 3
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.8V, 2.5V, 3.3V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.45V @ 150mA, 0.45V @ 150mA, 0.33V @ 150mA
- Current - Output:
- 200mA, 200mA, 200mA
- Current - Quiescent (Iq):
- 20 µA
- Current - Supply (Max):
- -
- PSRR:
- 55dB (1kHz)
- Control Features:
- Enable, Power On Reset
- Protection Features:
- Over Current, Over Temperature
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-MLF® (2.5x2.5)
MIC5373-SJGYMT-TR FAQ
1.How can I place an order for MIC5373-SJGYMT-TR through Aetrix?
Please submit a Request for Quotation (RFQ) for MIC5373-SJGYMT-TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIC5373-SJGYMT-TR reliable?
The price and inventory of MIC5373-SJGYMT-TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIC5373-SJGYMT-TR is usually 5 days.
3.What payment methods are accepted for MIC5373-SJGYMT-TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIC5373-SJGYMT-TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIC5373-SJGYMT-TR?
MIC5373-SJGYMT-TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIC5373-SJGYMT-TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIC5373-SJGYMT-TR?
For technical support, including MIC5373-SJGYMT-TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIC5373-SJGYMT-TR requirements.
6.How does Aetrix verify that MIC5373-SJGYMT-TR is sourced from the original manufacturer or authorized distributors?
All MIC5373-SJGYMT-TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIC5373-SJGYMT-TR meets industry standards.
7.What is the process for return or replacement of MIC5373-SJGYMT-TR?
All MIC5373-SJGYMT-TR units undergo pre-shipment inspection (PSI). If there is an issue with MIC5373-SJGYMT-TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIC5373-SJGYMT-TR part is unused and in its original packaging.
Return procedure for MIC5373-SJGYMT-TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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