Microchip Technology MIC5387-GMMYMT-TR
- Part No.:
- MIC5387-GMMYMT-TR
- Manufacturer:
- Microchip Technology
- Package:
- 6-UFDFN Exposed Pad, 6-TMLF®
- Datasheet:
-
MIC5387-GMMYMT-TR.pdf
- Description:
- IC REG LIN 1.8V/2.8V/2.8V 6TMLF
- Quantity:
- Payment:

- Shipping:

Inventory:4,925
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Product details
Overview
MIC5387-GMMYMT-TR from Micrel is a triple-output low-dropout linear regulator IC delivering 150mA per channel with fixed output voltages of 1.8V (OUT1), 2.8V (OUT2), and 2.8V (OUT3), housed in a 1.6mm × 1.6mm 6-pin Thin MLF® package. It features ±2% initial output accuracy, 180mV dropout at 150mA, 70dB PSRR at 1kHz, and operates across −40°C to +125°C - ideal for space-constrained portable electronics requiring independent, low-noise power rails.
For engineers reviewing the MIC5387-GMMYMT-TR datasheet, MIC5387-GMMYMT-TR pinout, MIC5387-GMMYMT-TR application, or MIC5387-GMMYMT-TR equivalent, key selection considerations include its shared enable input (EN2/3) controlling only OUT2 and OUT3, absence of enable on OUT1, ultra-low ground current (32µA per LDO), RoHS-compliant lead-free packaging, and stability with 1µF ceramic capacitors.
Technical Context
The MIC5387-GMMYMT-TR integrates three independent CMOS-based LDO regulators sharing a common input (VIN) and ground (GND), with EN2/3 enabling simultaneous control of the second and third outputs. Its architecture supports high PSRR via internal compensation optimized for 1µF ceramic output capacitors and maintains regulation down to zero load.
Thermal performance is governed by θJA = 92.4°C/W in the 1.6mm × 1.6mm Thin MLF® package, with internal thermal shutdown and current limiting (200–550mA) protecting all outputs. The device draws only 96–120µA total ground current under full 150mA load per output, enabling efficient operation in battery-powered systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltages | 1.8V (OUT1), 2.8V (OUT2), 2.8V (OUT3) - fixed, non-adjustable, enabling dual-rail 2.8V supply with auxiliary 1.8V logic rail |
| Max Output Current | 150mA per output - supports moderate-power digital cores, RF front-ends, or sensor interfaces without external pass devices |
| Dropout Voltage | 180mV @ 150mA (for VOUT ≥ 2.8V) - allows operation with ≤3.0V input when powering 2.8V rails, minimizing wasted headroom |
| PSRR | 70dB @ 1kHz - suppresses switching noise from upstream DC/DC converters, critical for analog/RF subsystems |
| Output Accuracy | ±2% initial, ±3% over −40°C to +125°C - ensures reliable voltage margining for 1.8V I/O and 2.8V analog circuits |
| Ground Current | 32µA per LDO (no load), 96–120µA total (full load) - extends battery life in always-on keep-alive or standby modes |
| Enable Control | EN2/3 active-high enables OUT2 & OUT3 only; OUT1 is always-on when VIN ≥ 2.5V - enables selective power sequencing |
Pinout & Package
Package: 6-pin 1.6mm × 1.6mm Thin MLF® (MT) with exposed thermal pad (EP) - RoHS-compliant, halogen-free, NiPdAu lead finish; occupies only 2.56mm² PCB area.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - GND | Common ground reference | Shared return path for all three LDOs; must connect to PCB ground plane for thermal and noise performance |
| 2 - VIN | Input supply node | Single input for all three regulators; requires 1µF X5R/X7R ceramic capacitor to ground for stability |
| 3 - EN2/3 | Active-high enable for OUT2 & OUT3 | CMOS-compatible logic input; must be pulled high (≥1.2V) to activate OUT2/OUT3; never float |
| 4 - OUT3 | Regulated 2.8V output | Second 2.8V rail; shares enable with OUT2; stable with ≥1µF ceramic capacitor |
| 5 - OUT2 | Regulated 2.8V output | First 2.8V rail; enabled by EN2/3; independent from OUT1; supports fast turn-on (50–125µs) |
| 6 - OUT1 | Regulated 1.8V output | Always-on 1.8V rail; no enable control; powers core logic or memory that must remain active during sleep |
| EP - HS Pad | Exposed heatsink pad | Internally connected to GND; solder to solid ground plane to reduce θJA and prevent thermal shutdown |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-small footprint | 1.6mm × 1.6mm Thin MLF® saves 36% board area vs. 2mm × 2mm MLF®, critical for slim mobile PCBs |
| Ceramic-capacitor stability | Guaranteed stable with 1µF X5R/X7R ceramics on all inputs/outputs - eliminates need for tantalum or electrolytic caps |
| No-load regulation | Maintains regulation at zero load - essential for CMOS RAM keep-alive, real-time clocks, and wake-on-event circuits |
| Integrated protection | Thermal shutdown + foldback current limiting (200–550mA) prevents damage during short-circuit or overload |
| Low-noise operation | 200µVRMS output noise (10Hz–100kHz) - suitable for powering ADCs, PLLs, and RF synthesizers |
Applications
| Mobile Phone Baseband | Digital Camera Sensor Core |
|---|---|
Use Scenario: Powering application processor I/O (1.8V), RF transceiver (2.8V), and PMIC interface (2.8V) in compact smartphone designs. IC Role / Device Role / Timing Role: Triple LDO providing isolated, low-noise, sequenced rails - OUT1 powers always-on logic; OUT2/OUT3 activated jointly during call mode. Use Value: Eliminates need for three discrete regulators, reducing BOM count and PCB area while maintaining PSRR >70dB to prevent RF coupling into baseband. |
Use Scenario: Supplying image sensor analog core (2.8V), digital interface (1.8V), and ISP block (2.8V) in ultra-thin camera modules. IC Role / Device Role / Timing Role: Single-package solution delivering matched 2.8V rails with tight tracking and independent 1.8V domain for digital logic. Use Value: Enables <2.56mm² power section footprint, critical for wafer-level camera packages where board area is at a premium. |
| GPS Receiver Front-End | PDA Application Processor |
Use Scenario: Powering GPS LNA (2.8V), crystal oscillator buffer (2.8V), and baseband controller I/O (1.8V) in handheld navigation units. IC Role / Device Role / Timing Role: Low-noise LDO supplying sensitive RF/analog circuitry while rejecting switching noise from main system DC/DC. Use Value: 70dB PSRR at 1kHz suppresses DC/DC ripple, improving GPS signal acquisition time and position accuracy. |
Use Scenario: Delivering core voltage (1.8V), memory I/O (2.8V), and peripheral interface (2.8V) in legacy PDA platforms with strict thermal limits. IC Role / Device Role / Timing Role: High-temperature-rated (−40°C to +125°C) triple LDO supporting extended outdoor operation and passive cooling. Use Value: Thermal shutdown and 92.4°C/W θJA allow continuous 450mA total output in sealed enclosures without forced airflow. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-output LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6217B182MR-G | Single 150mA LDO; 1.8V fixed; no multi-output capability; smaller 1.2mm × 1.2mm USP-4 package | Requires three separate ICs to replicate MIC5387-GMMYMT-TR's triple function - increases layout complexity and component count | Select when only one regulated rail is needed and minimal footprint is paramount |
| Ricoh RP512K282D-TR-F | Dual 200mA LDO (2.8V/2.8V); no 1.8V rail; includes independent enable per output; higher quiescent current (60µA per LDO) | Lacks dedicated 1.8V output - unsuitable for systems requiring mixed-voltage logic domains | Select when dual 2.8V rails with per-rail enable control outweigh need for integrated 1.8V supply |
Compared with Torex XC6217B182MR-G and Ricoh RP512K282D-TR-F, the MIC5387-GMMYMT-TR uniquely delivers matched 2.8V rails plus a dedicated 1.8V rail in one die, with lowest ground current (32µA per LDO) and smallest total footprint (2.56mm²), making it optimal for space- and power-constrained portable designs requiring three distinct voltage domains.
Availability
MIC5387-GMMYMT-TR is available at Aetrix Electronics and suitable for mobile phones, digital cameras, GPS receivers, and PDAs requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for MIC5387-GMMYMT-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Micrel Inc. was a U.S.-based semiconductor company specializing in power management, timing, and networking ICs before its acquisition by Microchip Technology in 2015.
The MIC5387 product line was designed for ultra-compact portable electronics requiring multiple low-noise, low-quiescent-current voltage rails in minimal PCB area - targeting mobile, imaging, and GPS applications where size and efficiency are critical.
FAQ
What are the fixed output voltages of the MIC5387-GMMYMT-TR?
The MIC5387-GMMYMT-TR provides three fixed output voltages: 1.8V on OUT1, and 2.8V on both OUT2 and OUT3. These values are laser-trimmed during manufacturing and cannot be adjusted externally. The marking code "8D7" on the package confirms this specific voltage combination, distinguishing it from other variants like MIC5387-SGFYMT (3.3V/1.8V/1.5V).
Does the MIC5387-GMMYMT-TR support independent enable control for each output?
No. The MIC5387-GMMYMT-TR has only one enable input: EN2/3 (Pin 3), which simultaneously controls OUT2 and OUT3. OUT1 is always enabled when VIN exceeds 2.5V and has no enable functionality. This design simplifies sequencing for dual-rail 2.8V loads while keeping the 1.8V logic rail permanently active - useful for real-time clock or memory backup circuits.
What capacitor types and values are required for stable operation of the MIC5387-GMMYMT-TR?
The MIC5387-GMMYMT-TR requires a 1µF X5R or X7R ceramic capacitor from VIN to GND, and 1µF X5R/X7R ceramic capacitors on each output (OUT1, OUT2, OUT3). Y5V and Z5U dielectrics are not recommended due to excessive capacitance loss over temperature. The device remains stable at zero load, eliminating need for minimum load resistors.
What is the thermal performance limit of the MIC5387-GMMYMT-TR in its 1.6mm × 1.6mm package?
The MIC5387-GMMYMT-TR has a junction-to-ambient thermal resistance (θJA) of 92.4°C/W in the 1.6mm × 1.6mm Thin MLF® package. With all three outputs delivering 150mA (total 450mA load) and typical voltage drops, power dissipation reaches ~0.375W. At maximum rated junction temperature (125°C), this limits maximum ambient operating temperature to approximately 90°C - achievable only with proper thermal pad soldering to a solid ground plane.
Is the MIC5387-GMMYMT-TR compatible with modern RoHS and REACH requirements?
Yes. The MIC5387-GMMYMT-TR is manufactured in a lead-free (RoHS-compliant) 1.6mm × 1.6mm Thin MLF® package with NiPdAu lead finish and halogen-free mold compound. It meets JEDEC J-STD-020 moisture sensitivity level 1 (MSL-1) and is rated for reflow up to 260°C for 10 seconds - fully compatible with standard lead-free PCB assembly processes.
MIC5387-GMMYMT-TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 6-UFDFN Exposed Pad, 6-TMLF®
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 3
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.8V, 2.8V, 2.8V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.38V @ 150mA, 0.31V @ 150mA, 0.31V @ 150mA
- Current - Output:
- 150mA, 150mA, 150mA
- Current - Quiescent (Iq):
- 40 µA
- Current - Supply (Max):
- 120 µA
- PSRR:
- 70dB ~ 60dB (1kHz ~ 10kHz), - , -
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TMLF® (1.6x1.6)
MIC5387-GMMYMT-TR FAQ
1.How can I place an order for MIC5387-GMMYMT-TR through Aetrix?
Please submit a Request for Quotation (RFQ) for MIC5387-GMMYMT-TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIC5387-GMMYMT-TR reliable?
The price and inventory of MIC5387-GMMYMT-TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIC5387-GMMYMT-TR is usually 5 days.
3.What payment methods are accepted for MIC5387-GMMYMT-TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIC5387-GMMYMT-TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIC5387-GMMYMT-TR?
MIC5387-GMMYMT-TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIC5387-GMMYMT-TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIC5387-GMMYMT-TR?
For technical support, including MIC5387-GMMYMT-TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIC5387-GMMYMT-TR requirements.
6.How does Aetrix verify that MIC5387-GMMYMT-TR is sourced from the original manufacturer or authorized distributors?
All MIC5387-GMMYMT-TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIC5387-GMMYMT-TR meets industry standards.
7.What is the process for return or replacement of MIC5387-GMMYMT-TR?
All MIC5387-GMMYMT-TR units undergo pre-shipment inspection (PSI). If there is an issue with MIC5387-GMMYMT-TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIC5387-GMMYMT-TR part is unused and in its original packaging.
Return procedure for MIC5387-GMMYMT-TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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