My Inquiry
My Account
NXP Semiconductors MIMX9351CVVXMAB
- Part No.:
- MIMX9351CVVXMAB
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- -
- Datasheet:
-
MIMX9351CVVXMAB.pdf
- Description:
- MIMX9351CVVXMAB
- Quantity:
- Payment:
- Shipping:
Inventory:154
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MIMX9351CVVXMAB from NXP Semiconductors is an industrial-grade dual-core Arm® Cortex®-A55 applications processor operating at up to 1.7 GHz, integrated with a Cortex®-M33 real-time core (250 MHz), dual Gigabit Ethernet (one with TSN), MIPI CSI-2 and DSI interfaces, and LPDDR4X support - deployed in smart HMI, industrial vision, and EV charging gateways.
For engineers reviewing the MIMX9351CVVXMAB datasheet, MIMX9351CVVXMAB pinout, MIMX9351CVVXMAB application, or MIMX9351CVVXMAB equivalent, key selection criteria include its single-A55-core configuration, 11 × 11 mm FCBGA306 package, industrial temperature range (–40°C to +105°C), GDET-disabled security fuse option, and absence of NPU acceleration - distinguishing it from NPU-enabled variants like MIMX9352CVVXMAB.
Technical Context
The MIMX9351CVVXMAB implements a heterogeneous compute architecture: one Cortex-A55 core handles high-level OS tasks (Linux/RTOS) while the Cortex-M33 manages deterministic real-time control, sensor monitoring, and low-power domain supervision. Its memory subsystem includes 640 KB on-chip RAM with ECC, 256 KB cluster L3 cache, and a 16-bit LPDDR4X interface supporting up to 2 GB with inline ECC.
Connectivity is segmented across dedicated domains: dual GbE controllers (one IEEE 1588/TSN-capable), two FlexCAN-FD modules, three uSDHC interfaces (eMMC 5.1, SDXC, SDIO), and eight LPUARTs - all managed via centralized IOMUXC and TRDC-enforced resource partitioning for secure multi-domain operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Single Arm® Cortex®-A55 @ up to 1.7 GHz + single Cortex®-M33 @ up to 250 MHz - enables asymmetric processing with Linux on A55 and real-time firmware on M33. |
| Memory Interface | 16-bit LPDDR4X/LPDDR4 with inline ECC - supports up to 2 GB DDR space and hardware error correction for industrial reliability. |
| Display & Camera | MIPI DSI (4-lane, 1080p60), MIPI CSI-2 (2-lane, 1080p30), LVDS Tx (4-lane, 1366×768p60) - enables direct connection to touch HMI panels and machine vision sensors. |
| Networking | Dual Gigabit Ethernet: one with Time-Sensitive Networking (TSN), AVB, and IEEE 1588; second with EEE and AVB - suitable for deterministic industrial gateway timing. |
| Security | Arm TrustZone-A/M, EdgeLock® secure enclave, TRDC with 16 domains, BBSM with secure RTC - provides hardware-isolated secure boot and runtime domain separation. |
| Package & Temp | FCBGA306, 11 × 11 mm, 0.5 mm pitch; industrial temperature grade (–40°C to +105°C junction) - qualified for harsh factory-floor and outdoor energy infrastructure environments. |
| Special Fuse | GDET disabled (B-suffix) - excludes General Debug Enable Trap; used where debug access must be permanently restricted per security policy. |
Pinout & Package
Package: 306-ball Fine-Pitch Chip Scale Ball Grid Array (FCBGA), 11 mm × 11 mm, 0.5 mm ball pitch, 1.15 mm maximum height. Thermal resistance RθJA = 22.5°C/W (JESD51-9, 2s2p board).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Core supply input | 1.0 V nominal (±5%) for Cortex-A55/M33 logic; requires tight regulation and local decoupling to meet dynamic current demands. |
| CLKIN1/CLKIN2 | External clock inputs | Accepts 24 MHz crystal or oscillator reference; CLKIN1 feeds system PLLs, CLKIN2 optional for secondary clock domains. |
| ONOFF | Power state control | Pulse-to-ground initiates ON/OFF transitions or software-triggered power-down; timeout-configurable via BBNSM_CTRL[BTN_TIMEOUT]. |
| POR_B | Power-on reset input | Active-low asynchronous reset; requires external pull-up to NVCC_BBSM_1P8; critical for deterministic boot initialization sequence. |
| RTC_XTALI/RTC_XTALO | Real-time clock oscillator | Supports 32.768 kHz crystal; internal weak amplifier requires board parasitic mitigation (<100 MΩ leakage) for reliable startup and accuracy. |
Key Features
| Feature | Design Value |
|---|---|
| Asymmetric Dual-Core Architecture | Separate A55 (application) and M33 (real-time) execution domains eliminate RTOS/Linux co-scheduling conflicts and reduce latency-critical ISR overhead. |
| Time-Sensitive Networking (TSN) | Hardware-accelerated IEEE 802.1AS/1Qbv/1Qci support in one GbE controller enables sub-millisecond deterministic packet scheduling for industrial automation synchronization. |
| Secure Boot & Domain Isolation | TRDC enforces 16 hardware-defined memory/resource domains; EdgeLock® enclave manages cryptographic keys and attestation without exposing secrets to application cores. |
| Industrial I/O Flexibility | Eight LPUARTs (up to 5 Mbps), eight LPI2C, eight LPSPI, two FlexCAN-FD, and two I3C modules allow concurrent legacy fieldbus, sensor, and actuator interfacing without external bridge ICs. |
| Camera & Display Integration | MIPI CSI-2 (2-lane, 200 MP/s pixel rate) + ISI pipeline + PXP graphics compositor enable full-stack vision preprocessing (scaling, rotation, color conversion) before A55 CPU involvement. |
Applications
| Industrial HMI | EV Charging Gateway |
|---|---|
|
Use Scenario: Touch-based operator interface for PLC-controlled machinery with real-time status visualization and firmware update capability. IC Role / Device Role / Timing Role: MIMX9351CVVXMAB serves as main application processor driving MIPI DSI display and handling USB/SD updates, while M33 monitors safety I/O and executes watchdog supervision. Use Value: Single-chip integration eliminates external microcontroller and display controller, reducing BOM count and PCB area by 35% versus discrete solutions. |
Use Scenario: Communication hub between OCPP backend, ISO 15118 EVSE stack, and local CAN-connected metering/control modules in AC/DC charging stations. IC Role / Device Role / Timing Role: MIMX9351CVVXMAB runs Linux-based OCPP stack on A55, processes CAN-FD telemetry via M33, and synchronizes time-critical events using TSN Ethernet. Use Value: Hardware TSN ensures <100 µs time sync jitter across charging station clusters, meeting IEC 61850-9-3 Class D requirements without external timing ICs. |
| Energy Grid Monitoring | Touchless Access Control |
|
Use Scenario: Edge analytics node in substation RTUs collecting waveform data from analog front-ends and transmitting time-stamped phasor measurements over secure Ethernet. IC Role / Device Role / Timing Role: MIMX9351CVVXMAB acquires ADC samples via SAR module, applies FFT in MPE, and stamps results using IEEE 1588 hardware timestamping on GbE. Use Value: On-die 12-bit SAR ADC (1 MS/s) and hardware timestamping eliminate need for external precision ADC and timing add-ons, cutting latency by 120 µs. |
Use Scenario: Contactless biometric terminal using IR camera and depth sensing for facial recognition in secure facility entry points. IC Role / Device Role / Timing Role: MIMX9351CVVXMAB captures 1080p30 video via MIPI CSI-2, performs neural inference (via external NPU or software fallback), and drives secure authentication over encrypted CAN-FD to door lock actuators. Use Value: Dual-camera interface support allows simultaneous RGB + IR stream capture, enabling liveness detection without secondary image sensor or bridge chip. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar applications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMX9352CVVXMAB | Dual Cortex-A55 cores (vs. single), includes NPU (256 MAC @ 1.0 GHz), same package/temp grade | Required for ML inference workloads (e.g., on-device anomaly detection); not needed for pure control/HMI tasks | Select MIMX9352CVVXMAB only if neural inference acceleration is mandatory; MIMX9351CVVXMAB reduces thermal load and software complexity when NPU is unused. |
| MIMX9331CVVXMAB | Three-core variant (1×A55 + 2×M33), no NPU, lower DDR bandwidth (3.2 GT/s vs. 3.7 GT/s), same package/temp | Better suited for deeply embedded control with multiple concurrent real-time threads; lacks TSN and one GbE port | Choose MIMX9331CVVXMAB for cost-sensitive, non-gateway applications requiring only one GbE and enhanced M33 concurrency - not for TSN or dual-network gateway roles. |
Compared with MIMX9352CVVXMAB, MIMX9351CVVXMAB trades NPU and dual-A55 capability for lower power, simpler thermal design, and reduced software stack complexity - ideal for deterministic HMI and gateway control where ML inference is offloaded or unnecessary. Against MIMX9331CVVXMAB, it delivers higher DDR throughput and full TSN support essential for synchronized industrial networking.
Availability
MIMX9351CVVXMAB is available at Aetrix Electronics and suitable for industrial HMI, EV charging infrastructure, and energy grid monitoring applications requiring stable component supply across extended product lifecycles and rigorous environmental qualification.
Supply support for MIMX9351CVVXMAB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure, power-efficient processing solutions for automotive, industrial, and IoT markets, with headquarters in Eindhoven, Netherlands.
The i.MX 93 family - including MIMX9351CVVXMAB - was designed specifically for industrial edge applications demanding functional safety, real-time responsiveness, and hardware-enforced security in harsh operating environments.
FAQ
What is the CPU configuration of the MIMX9351CVVXMAB?
The MIMX9351CVVXMAB integrates one Arm® Cortex®-A55 application processor core operating up to 1.7 GHz and one Arm® Cortex®-M33 real-time core running up to 250 MHz. This asymmetric dual-core architecture separates high-level OS execution from deterministic real-time control, enabling efficient task partitioning in industrial gateways and HMIs without requiring external microcontrollers.
Does the MIMX9351CVVXMAB include a Neural Processing Unit (NPU)?
No, the MIMX9351CVVXMAB does not include an NPU. Per Table 2 in the IMX93IEC datasheet, its "NPU" field is marked "Disabled". For NPU-enabled variants, consider MIMX9352CVVXMAB or MIMX9352CVVXMAC - both feature a 256-MAC NPU operating up to 1.0 GHz and optimized for 8-bit/16-bit integer inference workloads.
What package and thermal specifications apply to the MIMX9351CVVXMAB?
The MIMX9351CVVXMAB uses a 306-ball FCBGA package measuring 11 mm × 11 mm with 0.5 mm pitch. Its thermal resistance is RθJA = 22.5°C/W (JESD51-9, 2s2p board). This compact industrial-grade package supports operation from –40°C to +105°C junction temperature and is validated for use in convection-cooled industrial enclosures without forced airflow.
How does the MIMX9351CVVXMAB support Time-Sensitive Networking (TSN)?
The MIMX9351CVVXMAB includes one Gigabit Ethernet controller with full hardware support for IEEE 802.1AS (time sync), 802.1Qbv (time-aware shaper), and 802.1Qci (per-stream filtering), enabling sub-100 µs packet scheduling jitter. This TSN capability is implemented directly in the MAC layer and requires no software intervention - making it suitable for deterministic industrial automation networks.
What security features are enabled on the MIMX9351CVVXMAB given its 'B' fuse suffix?
The 'B' suffix in MIMX9351CVVXMAB indicates GDET (General Debug Enable Trap) is disabled - permanently restricting JTAG/SWD debug access after secure boot. All other hardware security features remain active: Arm TrustZone-A/M, EdgeLock® secure enclave, TRDC with 16 domains, BBSM with secure RTC, and on-chip RAM ECC - ensuring robust runtime isolation and secure boot integrity without debug surface exposure.
MIMX9351CVVXMAB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- -
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- -
- Number of Cores/Bus Width:
- -
- Speed:
- -
- Co-Processors/DSP:
- -
- RAM Controllers:
- -
- Graphics Acceleration:
- -
- Display & Interface Controllers:
- -
- Ethernet:
- -
- SATA:
- -
- USB:
- -
- Voltage - I/O:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
- Additional Interfaces:
- -
MIMX9351CVVXMAB FAQ
1.How can I place an order for MIMX9351CVVXMAB through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMX9351CVVXMAB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMX9351CVVXMAB reliable?
The price and inventory of MIMX9351CVVXMAB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMX9351CVVXMAB is usually 5 days.
3.What payment methods are accepted for MIMX9351CVVXMAB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIMX9351CVVXMAB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIMX9351CVVXMAB?
MIMX9351CVVXMAB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMX9351CVVXMAB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMX9351CVVXMAB?
For technical support, including MIMX9351CVVXMAB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMX9351CVVXMAB requirements.
6.How does Aetrix verify that MIMX9351CVVXMAB is sourced from the original manufacturer or authorized distributors?
All MIMX9351CVVXMAB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMX9351CVVXMAB meets industry standards.
7.What is the process for return or replacement of MIMX9351CVVXMAB?
All MIMX9351CVVXMAB units undergo pre-shipment inspection (PSI). If there is an issue with MIMX9351CVVXMAB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMX9351CVVXMAB part is unused and in its original packaging.
Return procedure for MIMX9351CVVXMAB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MIMX9351CVVXMAB Tags
-
AT91SAM9260B-CU-999
Microchip Technology
-
AT91SAM9G25-CU
Microchip Technology
-
ATSAMA5D27C-CU
Microchip Technology
-
AT91SAM9X35-CU
Microchip Technology
-
AT91SAM9X25-CU
Microchip Technology
-
MCIMX6Y2CVM08AB
NXP Semiconductors
.JPG)
-
AM3352BZCZ100
Texas Instruments
-
AT91SAM9260B-CU
Microchip Technology
-
AT91SAM9260B-QU
Microchip Technology
-
ATSAMA5D31A-CU
Microchip Technology
-
AT91SAM9G20B-CU-999
Microchip Technology
-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
