NXP Semiconductors MIMX9352CVTXMAB
- Part No.:
- MIMX9352CVTXMAB
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 306-LFBGA, FCBGA
- Datasheet:
-
MIMX9352CVTXMAB.pdf
- Description:
- MIMX9352CVTXMAB
- Quantity:
- Payment:

- Shipping:

Inventory:4,275
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MIMX9352CVTXMAB from NXP Semiconductors is an industrial-grade dual-core Arm® Cortex®-A55 applications processor with integrated Neural Processing Unit (NPU), operating up to 1.7 GHz, supporting LPDDR4X with inline ECC, dual Gigabit Ethernet (one with TSN), and MIPI CSI-2/DSI interfaces - deployed in industrial HMI, vision systems, and EV charging gateways.
For engineers reviewing the MIMX9352CVTXMAB datasheet, MIMX9352CVTXMAB pinout, MIMX9352CVTXMAB application, or MIMX9352CVTXMAB equivalent, this page delivers verified specifications, package mapping, validated alternatives, and design-critical interface behavior for industrial edge deployment under -40°C to +105°C conditions.
Technical Context
The MIMX9352CVTXMAB implements a heterogeneous compute architecture: two Cortex-A55 cores (1.7 GHz) handle Linux-based application workloads, while a dedicated Cortex-M33 core (250 MHz) manages real-time control, low-power monitoring, and secure boot orchestration. The on-die NPU delivers 256 MACs at 1.0 GHz for integer RNN inference.
It integrates dual 1 Gbps Ethernet controllers - one compliant with IEEE 802.1AS/TSN for deterministic networking - alongside FlexCAN-FD, I3C, LPUART, and MIPI interfaces. Memory subsystem includes 640 KB on-chip RAM with ECC, 256 KB cluster L3 cache, and a 16-bit LPDDR4X interface supporting up to 2 GB with inline ECC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual Arm® Cortex®-A55 @ up to 1.7 GHz - enables concurrent Linux application execution and real-time responsiveness in industrial gateways. |
| NPU | 256 MACs @ 1.0 GHz, 2 OPS/MAC - accelerates 8-bit/16-bit integer neural network inference for on-device ML in vision or anomaly detection. |
| Memory Interface | 16-bit LPDDR4X/LPDDR4 with inline ECC - supports up to 2 GB DDR space with error correction for mission-critical industrial operation. |
| Ethernet | Dual 1 Gbps controllers: one with IEEE 1588/AVB/EEE; second with full TSN support - enables time-synchronized multi-protocol industrial networking. |
| Camera & Display | 2-lane MIPI CSI-2 (up to 1080p30); 4-lane MIPI DSI (up to 1080p60) - supports embedded vision input and high-resolution touch HMI output. |
| Security | Arm TrustZone-A/M, EdgeLock® secure enclave, TRDC with 16 domains, BBSM with secure RTC - meets industrial functional safety and data integrity requirements. |
| Package | 14 × 14 mm, 0.65 mm pitch FCBGA306 - industrial thermal profile (RθJA = 21.7°C/W) suitable for convection-cooled enclosures. |
Pinout & Package
Package: 14 × 14 mm, 0.65 mm pitch Fine-Pitch Ball Grid Array (FCBGA306), industrial temperature grade (-40°C to +105°C junction).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Core supply voltage | 1.0 V ± 3% nominal; absolute max 1.15 V - powers Cortex-A55/M33 cores and L1/L2 caches; requires tight regulation for stability at 1.7 GHz. |
| CLKIN1/CLKIN2 | External clock inputs | No internal pull-up/down; external 10 kΩ pull-down required if unused - critical for system clock tree integrity and USB timing compliance. |
| ONOFF | Power state control | Active-low momentary signal: short pulse triggers ON/OFF transitions; long press forces forced OFF - enables hardware-controlled power sequencing without PMIC dependency. |
| POR_B | Power-on reset input | Requires external pull-up to NVCC_BBSM_1P8 - ensures reliable reset assertion during cold start and brown-out recovery in industrial environments. |
| RTC_XTALI/RTC_XTALO | Real-time clock oscillator pins | Self-biasing 32.768 kHz crystal interface; board parasitics must be compensated - ensures tamper-resistant, battery-backed timekeeping for logging and scheduling. |
Key Features
| Feature | Design Value |
|---|---|
| Heterogeneous Core Architecture | Dual Cortex-A55 + Cortex-M33 enables Linux + RTOS coexistence - eliminates need for companion microcontroller in industrial gateway designs. |
| Time-Sensitive Networking (TSN) | Hardware-accelerated IEEE 802.1AS/1Qbv/1Qbu - guarantees sub-millisecond latency and jitter control for synchronized motion control or sensor fusion. |
| Secure Boot & Domain Isolation | EdgeLock® enclave + TRDC + TrustZone-A/M - enforces hardware-rooted chain of trust and memory-protected resource partitioning across firmware, OS, and application layers. |
| Industrial I/O Flexibility | 8x LPUART (up to 5 Mbps), 8x LPI2C, 8x LPSPI, 2x FlexCAN-FD, 2x I3C - supports legacy fieldbus bridging (Modbus RTU over UART) and modern sensor aggregation. |
| Imaging Pipeline Acceleration | ISI + PXP + LCDIF - enables real-time 2K image capture, downscaling, color conversion, and display composition without CPU load in vision-guided automation. |
Applications
| Industrial HMI | EV Charging Gateway |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with real-time status visualization and firmware update capability. IC Role / Device Role / Timing Role: Primary applications processor executing Linux Qt-based GUI, managing MIPI DSI display, LVDS touchscreen controller, and secure OTA updates via Ethernet. Use Value: Dual A55 cores ensure smooth 60 Hz UI rendering while M33 handles CAN-FD communication with motor drives - eliminating latency between user input and actuator response. |
Use Scenario: Smart AC/DC charging station coordinating grid communication (IEC 61850), vehicle handshake (ISO 15118), and local energy metering. IC Role / Device Role / Timing Role: Central gateway SoC running real-time charging stack on Cortex-M33 and Linux-based cloud agent on Cortex-A55, with TSN-synchronized metering data acquisition. Use Value: Integrated TSN Ethernet ensures precise timestamping of energy consumption events aligned with utility billing cycles - meeting IEC 62056-21 accuracy requirements. |
| Industrial Vision System | Touchless Access Control |
Use Scenario: Embedded vision node performing real-time barcode scanning, defect detection, and OCR in packaging lines or logistics hubs. IC Role / Device Role / Timing Role: Image sensor interface (MIPI CSI-2) feeds raw frames to NPU for inference; PXP performs pre-processing; LCDIF drives local status display. Use Value: On-die NPU achieves >30 FPS 1080p inference at <2 W - avoids external AI accelerator, reducing BOM cost and thermal footprint in sealed enclosures. |
Use Scenario: Contactless entry terminal using facial recognition or gesture control in cleanroom or healthcare environments. IC Role / Device Role / Timing Role: Secure boot-enforced isolation between biometric capture (PDM mic array + ISI), encrypted template storage (OCRAM), and access decision logic (M33). Use Value: EdgeLock® secure enclave protects biometric templates from extraction - satisfies ISO/IEC 30107-3 liveness detection and GDPR biometric data handling mandates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar applications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMX9352CVVXMAB | Same dual-core A55/NPU/TSN feature set but in 11 × 11 mm FCBGA306 package (0.5 mm pitch) - lower thermal resistance (RθJA = 22.5°C/W) but reduced PCB routing margin. | Preferred for space-constrained HMI panels where thermal headroom exceeds 1.5 W; not suitable for high-ambient EV charging enclosures requiring 14 mm package thermal derating. | Select when board area is primary constraint and industrial ambient remains ≤85°C - verify ball map compatibility with existing layout. |
| i.MX 8M Plus (MIMX8ML8CVNKZ) | Quad-core Cortex-A53 + NPU (2.3 TOPS), no TSN Ethernet, older 14 nm process - higher static power, lacks dual-GbE with AVB/TSN, no Cortex-M33 real-time domain. | Suitable for non-deterministic multimedia gateways (e.g., digital signage), but cannot replace MIMX9352CVTXMAB in time-critical industrial control or EVSE synchronization. | Consider only for cost-sensitive, non-TSN applications where Linux GUI performance dominates over real-time determinism and security depth. |
Compared with MIMX9352CVTXMAB, the MIMX9352CVVXMAB offers identical functionality in a smaller package with tighter pitch, while the i.MX 8M Plus provides higher NPU throughput but lacks TSN, secure domain isolation, and industrial thermal robustness - making MIMX9352CVTXMAB the sole fit for deterministic, secure, thermally demanding industrial edge deployments.
Availability
MIMX9352CVTXMAB is available at Aetrix Electronics and suitable for industrial human-machine interface (HMI), EV charging infrastructure, and smart building gateway applications requiring stable component supply across extended product lifecycles.
Supply support for MIMX9352CVTXMAB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure, connected, and intelligent edge solutions for automotive, industrial, and IoT markets.
The i.MX 93 family - including MIMX9352CVTXMAB - was designed specifically for power-optimized, secure, and time-deterministic industrial edge processing, integrating AI acceleration, TSN networking, and hardware-enforced security into a single SoC.
FAQ
What is the maximum operating temperature range for the MIMX9352CVTXMAB?
The MIMX9352CVTXMAB is rated for industrial temperature operation from -40°C to +105°C junction temperature. This specification is confirmed in the i.MX 93 Applications Processors Data Sheet for Industrial Products (IMX93IEC, Rev. 8), and the 14 × 14 mm FCBGA306 package delivers RθJA = 21.7°C/W under JEDEC JESD51-9 test conditions - enabling reliable operation in unventilated industrial enclosures.
Does the MIMX9352CVTXMAB support Time-Sensitive Networking (TSN)?
Yes, the MIMX9352CVTXMAB includes hardware-accelerated TSN support in its second Gigabit Ethernet controller, compliant with IEEE 802.1AS (time synchronization), 802.1Qbv (time-aware shaper), and 802.1Qbu (frame preemption). This capability is documented in Section 1.1 and Table 1 of the IMX93IEC datasheet and is distinct from the first Ethernet port's AVB/EEE support.
What memory types and capacities does the MIMX9352CVTXMAB support?
The MIMX9352CVTXMAB supports 16-bit LPDDR4X and LPDDR4 with inline ECC, addressing up to 2 GB of external DRAM space. It also integrates 640 KB on-chip RAM (OCRAM) with ECC protection, 256 KB cluster L3 cache, and separate 256 KB boot ROM for both Cortex-A55 and Cortex-M33 - all verified in Tables 1 and 2 of the IMX93IEC datasheet.
Is the Neural Processing Unit (NPU) enabled on the MIMX9352CVTXMAB?
Yes, the MIMX9352CVTXMAB includes a fully enabled NPU delivering 256 MACs operating up to 1.0 GHz and 2 OPS/MAC, optimized for 8-bit and 16-bit integer RNN inference. This is explicitly stated in Table 2 ("NPU" column = "NPU") and Table 1 ("Neural Processing Unit") of the IMX93IEC datasheet - distinguishing it from NPU-disabled variants like MIMX9332CVTXMAC.
What camera and display interfaces are supported by the MIMX9352CVTXMAB?
The MIMX9352CVTXMAB supports a 2-lane MIPI CSI-2 interface (up to 1080p30), parallel camera input, 4-lane MIPI DSI (up to 1080p60), 4-lane LVDS, and parallel RGB display outputs - as specified in Table 2 of the IMX93IEC datasheet under "Camera" and "Display" columns. These interfaces are physically implemented and electrically characterized per Figures 2 and 3 in the same document.
MIMX9352CVTXMAB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 306-LFBGA, FCBGA
- Series:
- i.MX 93
- Packaging:
- Bulk
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A55, ARM® Cortex®-M33
- Number of Cores/Bus Width:
- 2, 1 Core, 64-Bit
- Speed:
- 250MHz, 1.7GHz
- Co-Processors/DSP:
- Multimedia; NEON™ MPE
- RAM Controllers:
- LPDDR4
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- LCD, LVDS, MIPI-CSI, MIPI-DSI
- Ethernet:
- GBE (2)
- SATA:
- -
- USB:
- USB 2.0 (2)
- Voltage - I/O:
- 1.8V
- Operating Temperature:
- -40°C ~ 105°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- Boot Security, Cryptography, eFuse, Random Number Generator, Secure RTC, Tamper Detection
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 306-FCBGA (14x14)
- Additional Interfaces:
- CANbus, DMA, GPIO, I2C, I2S, MMC/SD/SDIO, PCIe, QSPI, SAI, SPDIF, SPI, UART
MIMX9352CVTXMAB FAQ
1.How can I place an order for MIMX9352CVTXMAB through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMX9352CVTXMAB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMX9352CVTXMAB reliable?
The price and inventory of MIMX9352CVTXMAB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMX9352CVTXMAB is usually 5 days.
3.What payment methods are accepted for MIMX9352CVTXMAB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIMX9352CVTXMAB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIMX9352CVTXMAB?
MIMX9352CVTXMAB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMX9352CVTXMAB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMX9352CVTXMAB?
For technical support, including MIMX9352CVTXMAB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMX9352CVTXMAB requirements.
6.How does Aetrix verify that MIMX9352CVTXMAB is sourced from the original manufacturer or authorized distributors?
All MIMX9352CVTXMAB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMX9352CVTXMAB meets industry standards.
7.What is the process for return or replacement of MIMX9352CVTXMAB?
All MIMX9352CVTXMAB units undergo pre-shipment inspection (PSI). If there is an issue with MIMX9352CVTXMAB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMX9352CVTXMAB part is unused and in its original packaging.
Return procedure for MIMX9352CVTXMAB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MIMX9352CVTXMAB Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

