NXP Semiconductors MIMX9352CVVXMAB
- Part No.:
- MIMX9352CVVXMAB
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 306-LFBGA
- Datasheet:
-
MIMX9352CVVXMAB.pdf
- Description:
- MIMX9352CVVXMAB
- Quantity:
- Payment:

- Shipping:

Inventory:2,498
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MIMX9352CVVXMAB from NXP Semiconductors is an industrial-grade dual-core Arm® Cortex®-A55 applications processor with integrated Neural Processing Unit (NPU), operating up to 1.7 GHz, supporting LPDDR4X/LPDDR4 with inline ECC, dual Gigabit Ethernet (one with TSN), and MIPI CSI-2/DSI interfaces - deployed in industrial HMI, vision systems, and EV charging gateways.
For engineers reviewing the MIMX9352CVVXMAB datasheet, MIMX9352CVVXMAB pinout, MIMX9352CVVXMAB application, or MIMX9352CVVXMAB equivalent, key selection criteria include its 11 × 11 mm FCBGA306 package, industrial temperature range (−40°C to +105°C), dual-A55 + M33 heterogeneous architecture, NPU acceleration for edge ML inference, and TSN-capable Ethernet for deterministic networking.
Technical Context
The MIMX9352CVVXMAB implements a heterogeneous compute architecture: two Cortex-A55 cores (1.7 GHz) handle high-throughput Linux-based application workloads, while a dedicated Cortex-M33 core (250 MHz) manages real-time control, power state coordination, and secure boot services - all sharing coherent cache hierarchy and protected memory domains via Arm TrustZone-A/M.
Its connectivity stack includes two FlexCAN-FD controllers, dual GbE with IEEE 1588/TSN support, three uSDHC interfaces (eMMC 5.1/SDXC/SDIO), and dual USB 2.0 PHYs; multimedia subsystems comprise MIPI CSI-2 (2-lane, 1080p30), MIPI DSI (4-lane, 1080p60), LVDS Tx, and PXP-based 2D graphics acceleration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual Arm® Cortex®-A55 @ up to 1.7 GHz - enables concurrent Linux application execution with hardware virtualization support |
| Real-time Core | Arm® Cortex®-M33 @ up to 250 MHz - handles low-latency control, sensor fusion, and secure firmware runtime |
| NPU Performance | 256 MACs @ 1.0 GHz (2 OPS/MAC) - delivers ~512 GOPS integer inference for 8-bit/16-bit RNNs at edge |
| Memory Interface | 16-bit LPDDR4X/LPDDR4 with inline ECC - supports up to 2 GB DDR space with error correction for industrial reliability |
| Display Interfaces | MIPI DSI (4-lane), LVDS Tx (4-lane), parallel RGB - drives 1080p60 displays with hardware composition via PXP |
| Camera Interface | MIPI CSI-2 (2-lane, 1.5 Gbps/lane) + parallel YUV/RGB - supports 1080p30 imaging with on-chip ISI preprocessing |
| Networking | Dual Gigabit Ethernet: one with TSN/IEEE 1588, one with AVB/EEE - enables time-synchronized gateway and control plane separation |
| Package & Temp | FCBGA306, 11 × 11 mm, 0.5 mm pitch; industrial grade (−40°C to +105°C junction) |
Pinout & Package
Package: 306-ball Fine-Pitch Ball Grid Array (FCBGA), 11 mm × 11 mm, 0.5 mm ball pitch, 0.8 mm nominal height. Thermal pad exposed on underside for PCB-level heat dissipation. Compatible with standard reflow profiles for Pb-free assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Core supply rail | 1.0 V ±3% input for Cortex-A55/M33 clusters and L2/L3 caches - requires low-noise regulation and local decoupling |
| NVCC_GPIO | GPIO I/O supply | Configurable 1.8 V / 3.3 V bank supply - sets logic threshold for 32 GPIOs with interrupt capability |
| XTALI_24M / XTALO_24M | Main system oscillator input/output | 24 MHz crystal reference for PLLs - mandatory for USB clock derivation and system timing stability |
| RTC_XTALI / RTC_XTALO | Real-time clock oscillator | 32.768 kHz crystal interface for battery-backed RTC - requires <50 kΩ board leakage and external load capacitors |
| ONOFF | Power state control | Active-low momentary button input - triggers ON/OFF transitions and software-initiated power-down via BBSM |
| POR_B | Power-on reset input | Asynchronous reset assertion - must be pulled up to NVCC_BBSM_1P8; governs boot sequence initialization |
Key Features
| Feature | Design Value |
|---|---|
| EdgeLock® Secure Enclave | Hardware-isolated security domain with cryptographic accelerators, eFuse key storage, and tamper detection - enforces secure boot, attestation, and key lifecycle management |
| Unified Trace & Debug | CoreSight™ infrastructure with ETF (4 KB) and CTI - enables synchronized trace capture across A55 and M33 cores for complex firmware validation |
| Flexible Power Domains | Per-subsystem power gating controlled by TRDC - allows independent shutdown of display, camera, or Ethernet blocks to reduce idle power below 100 mW |
| Audio Subsystem | Three SAI interfaces (7x I²S/TDM channels), SPDIF, and 8-mic PDM input - supports multi-channel voice processing and echo cancellation without external codecs |
| Industrial Connectivity | Two FlexCAN-FD controllers, eight LPUARTs (up to 5 Mbps), and two I3C modules - meets CAN FD timing requirements and enables daisy-chain sensor networks |
Applications
| Industrial HMI | Smart EV Charging Station |
|---|---|
|
Use Scenario: Touch-enabled panel with real-time status visualization, payment integration, and remote diagnostics in factory environments. IC Role / Device Role / Timing Role: Main applications processor executing Linux GUI stack, managing CAN-FD communication with charging modules, and synchronizing TSN Ethernet for cloud telemetry. Use Value: Dual A55 cores ensure responsive UI rendering while M33 handles CAN message scheduling and safety-critical state monitoring - eliminating need for separate microcontroller. |
Use Scenario: AC/DC charging station requiring OCPP 1.6/2.0 protocol handling, energy metering, and secure OTA updates over cellular backhaul. IC Role / Device Role / Timing Role: Central gateway SoC running embedded Linux, interfacing with ISO 15118-compliant PLC modems, and timestamping energy data via IEEE 1588 PTP. Use Value: Integrated TSN Ethernet enables deterministic latency for grid synchronization signals; EdgeLock enclave secures firmware signing keys and metering data integrity. |
| Machine Vision Gateway | Touchless Access Control |
|
Use Scenario: Edge vision node capturing 1080p30 video from multiple cameras, performing barcode/QR decoding and anomaly detection before forwarding metadata. IC Role / Device Role / Timing Role: Image sensor interface (ISI) preprocessor feeding raw frames to NPU for lightweight CNN inference; PXP performs real-time scaling and color conversion. Use Value: On-die NPU achieves >30 FPS 8-bit INT8 inference on ResNet-18 variants - avoids external AI accelerator and reduces BOM cost and thermal load. |
Use Scenario: Contactless entry system using facial recognition and gesture control in healthcare or cleanroom facilities. IC Role / Device Role / Timing Role: Real-time face detection on MIPI CSI-2 input, secure biometric template storage in OCRAM, and low-power wake-on-motion via M33. Use Value: Hardware-accelerated PXP and NPU enable sub-100ms end-to-end latency from image capture to access decision - critical for user experience and hygiene compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar applications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMX9352CVTXMAC | Larger 14 × 14 mm FCBGA306 package (0.65 mm pitch); identical core/NPU/Ethernet specs | Better thermal performance (RθJA = 21.7°C/W vs. 22.5°C/W); suitable for higher ambient or sustained load scenarios | Select when board layout allows larger footprint and thermal margin is prioritized over compactness |
| MIMX9332CVVXMAB | Dual A55 cores at 1.7 GHz but no NPU; same 11 × 11 mm package and industrial temp grade | Lower cost for non-AI applications; lacks neural inference acceleration but retains full display/camera/Ethernet functionality | Choose when ML inference is unnecessary and BOM cost reduction is critical without sacrificing industrial reliability |
Compared with MIMX9352CVVXMAB, MIMX9352CVTXMAC offers improved thermal dissipation in space-permitting designs, while MIMX9332CVVXMAB removes NPU silicon to lower unit cost - both retain identical peripheral sets and industrial qualification, enabling direct migration within the i.MX 93 family.
Availability
MIMX9352CVVXMAB is available at Aetrix Electronics and suitable for industrial HMI, smart EV charging infrastructure, and machine vision gateway designs requiring stable component supply, long-term industrial qualification, and NPU-accelerated edge intelligence.
Supply support for MIMX9352CVVXMAB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, IoT, and mobile applications - headquartered in Eindhoven, Netherlands.
The i.MX 93 family, including MIMX9352CVVXMAB, was designed specifically for power-constrained industrial edge devices requiring real-time responsiveness, AI inferencing, and robust functional safety - targeting HMI, vision, and gateway use cases demanding ASIL-B readiness and extended temperature operation.
FAQ
What is the maximum operating frequency of the Cortex-A55 cores in the MIMX9352CVVXMAB?
The MIMX9352CVVXMAB features two Arm® Cortex®-A55 application processor cores rated for operation up to 1.7 GHz under industrial temperature conditions (−40°C to +105°C). This frequency is guaranteed with proper thermal management and compliant power delivery per the IMX93IEC datasheet specifications. The MIMX9352CVVXMAB maintains this speed across its full industrial operating range when supplied with stable 1.0 V ±3% VDD_SOC and adequate PCB thermal design.
Does the MIMX9352CVVXMAB include hardware support for Time-Sensitive Networking (TSN)?
Yes, the MIMX9352CVVXMAB integrates one Gigabit Ethernet controller with full IEEE 802.1AS, 802.1Qbv, and 802.1Qbu TSN support, including hardware timestamping, time-aware shaper, and frame preemption. This TSN-capable Ethernet port operates alongside a second GbE controller supporting AVB and EEE - enabling deterministic traffic scheduling essential for industrial automation and synchronized gateway applications using the MIMX9352CVVXMAB.
What camera interfaces does the MIMX9352CVVXMAB support, and what resolutions are achievable?
The MIMX9352CVVXMAB supports MIPI CSI-2 (2-lane, up to 1.5 Gbps per lane) and parallel YUV/RGB camera inputs. With its Image Sensor Interface (ISI), it processes up to 1080p30 video (200 MPixel/s pixel rate) and performs on-the-fly downscaling, color space conversion, and interlaced-to-progressive conversion. The MIMX9352CVVXMAB does not support MIPI CSI-2 v2.0 or 4-lane configurations - its camera capability is strictly defined by the MIX93IEC datasheet for this variant.
Is the Neural Processing Unit (NPU) enabled in the MIMX9352CVVXMAB, and what precision does it support?
Yes, the MIMX9352CVVXMAB includes a fully enabled Neural Processing Unit (NPU) delivering 512 GOPS peak integer performance at 1.0 GHz. It supports 8-bit and 16-bit integer RNN inference with 8-bit weight quantization, optimized for edge ML models such as MobileNetV2 and Tiny-YOLO. The NPU is accessible via NXP's eIQ™ Toolkit and integrated into the Linux BSP - confirming that the MIMX9352CVVXMAB provides production-ready AI acceleration without external coprocessors.
What is the package type and ball count for the MIMX9352CVVXMAB?
The MIMX9352CVVXMAB uses a 306-ball Fine-Pitch Ball Grid Array (FCBGA) package measuring 11 mm × 11 mm with 0.5 mm ball pitch. This package is designated "VV" in NXP's part numbering nomenclature and is qualified for industrial temperature operation (−40°C to +105°C). The MIMX9352CVVXMAB's FCBGA306 footprint is documented in the i.MX 93 Applications Processor Reference Manual and supported by NXP's official EVK design files.
MIMX9352CVVXMAB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 306-LFBGA
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A55, ARM® Cortex®-M33
- Number of Cores/Bus Width:
- 2 Core, 64-Bit
- Speed:
- 250MHz
- Co-Processors/DSP:
- Multimedia; NEON
- RAM Controllers:
- LPDDR4, LPDDR4x
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- LCD, MIPI-CSI2, MIPI-DSI
- Ethernet:
- 10/100/1000Mbps
- SATA:
- -
- USB:
- USB 2.0 (2)
- Voltage - I/O:
- 1.0V, 1.1V
- Operating Temperature:
- -40°C ~ 105°C (TJ)
- Grade:
- Automotive
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 306-LFBGA (11x11)
- Additional Interfaces:
- CAN, DUART, I2C, MMC/SD, SPI, TDM
MIMX9352CVVXMAB FAQ
1.How can I place an order for MIMX9352CVVXMAB through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMX9352CVVXMAB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMX9352CVVXMAB reliable?
The price and inventory of MIMX9352CVVXMAB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMX9352CVVXMAB is usually 5 days.
3.What payment methods are accepted for MIMX9352CVVXMAB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIMX9352CVVXMAB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIMX9352CVVXMAB?
MIMX9352CVVXMAB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMX9352CVVXMAB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMX9352CVVXMAB?
For technical support, including MIMX9352CVVXMAB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMX9352CVVXMAB requirements.
6.How does Aetrix verify that MIMX9352CVVXMAB is sourced from the original manufacturer or authorized distributors?
All MIMX9352CVVXMAB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMX9352CVVXMAB meets industry standards.
7.What is the process for return or replacement of MIMX9352CVVXMAB?
All MIMX9352CVVXMAB units undergo pre-shipment inspection (PSI). If there is an issue with MIMX9352CVVXMAB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMX9352CVVXMAB part is unused and in its original packaging.
Return procedure for MIMX9352CVVXMAB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MIMX9352CVVXMAB Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

