My Inquiry
My Account
NXP Semiconductors MIMXRT1024DAG5B
- Part No.:
- MIMXRT1024DAG5B
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
MIMXRT1024DAG5B.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 144LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,019
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MIMXRT1024DAG5B from NXP Semiconductors is a consumer-grade Arm® Cortex®-M7 crossover processor operating at 500 MHz, integrating 4 MB on-chip flash, 256 KB configurable on-chip RAM (TCM/OCRAM), and dual FlexCAN interfaces. It delivers real-time deterministic performance for motor control, industrial HMI, and IoT edge nodes requiring integrated security, audio, and Ethernet connectivity.
For engineers reviewing the MIMXRT1024DAG5B datasheet, MIMXRT1024DAG5B pinout, MIMXRT1024DAG5B application, or MIMXRT1024DAG5B equivalent, key selection criteria include its 144-pin LQFP package with 90 GPIOs, 500 MHz core frequency, integrated DCDC/LDO power management, and support for SAI, SPDIF, USB OTG, and IEEE 1588–enabled 10/100 ENET.
Technical Context
The MIMXRT1024DAG5B implements a single Arm Cortex-M7 core with 16 KB I-cache, 16 KB D-cache, and full VFPv5 FPU - enabling high-throughput signal processing and real-time control loops. Its memory subsystem includes boot ROM (96 KB), 4 MB flash with XIP support, and 256 KB FlexRAM configurable as I-TCM/D-TCM/OCRAM in 32 KB granularity.
Peripherals are organized via centralized IOMUXC with pin multiplexing; it integrates two FlexPWM modules (8 channels total, 16-bit resolution), two Quad Timers with quadrature decoding, dual eMMC/SDHC controllers (up to 100 MB/s), and hardware-accelerated security including HAB, DCP (AES-128/SHA-256), BEE, and SNVS with secure RTC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | Arm Cortex-M7 @ 500 MHz - enables deterministic real-time execution with FPU and MPU for safety-critical control tasks. |
| On-chip Memory | 4 MB flash + 256 KB FlexRAM - eliminates external flash need; RAM configurable as TCM for low-latency code/data access. |
| Package & Pin Count | 144-pin LQFP, 20 × 20 mm, 0.5 mm pitch - supports 90 GPIOs with full IOMUX flexibility for industrial I/O expansion. |
| Connectivity | Dual FlexCAN 2.0B, 10/100 ENET with IEEE 1588, USB OTG (HS PHY), 2× uSDHC (eMMC 4.5/SD 3.0) - enables robust fieldbus, time-synchronized networking, and high-speed local storage. |
| Audio Interfaces | 3× SAI (I2S/TDM/AC97), SPDIF Tx/Rx, MQS - supports multi-channel audio playback, voice interface, and digital audio transport without external codecs. |
| Analog Peripherals | 2× 12-bit ADC (19-channel), 4× analog comparators, temperature sensor - provides direct sensor interfacing for motor current sensing, thermal monitoring, and analog feedback. |
| Security Features | HAB, DCP (AES-128/SHA-256), BEE (on-the-fly QSPI decryption), SNVS with secure RTC - enables secure boot, encrypted firmware updates, and tamper-resistant timekeeping. |
Pinout & Package
144-pin LQFP package (20 × 20 mm, 0.5 mm pitch) with exposed pad for thermal dissipation. Pin assignments follow NXP's i.MX RT1024 Reference Manual (IMXRT1024RM) and datasheet Section 7. Contact assignments are validated per Table 7-1 (page 80) of IMXRT1024CEC Rev. 2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Core logic supply | 1.0–1.3 V input for Cortex-M7 core and internal peripherals; requires tight regulation and local decoupling. |
| DCDC_IN | DCDC converter input | 3.3 V input feeding on-chip DCDC; enables single-rail power design and eliminates external buck regulator. |
| XTALI / XTALO | 24 MHz crystal oscillator inputs | Drive system clock generation; requires 24 MHz crystal with load capacitance matching per layout guidelines. |
| RTC_XTALI / RTC_XTALO | 32.768 kHz RTC oscillator inputs | Enable precision real-time clock; optional crystal connection or internal ring oscillator fallback. |
| ENET_RXD0–3 / TXD0–3 | Ethernet physical layer interface | Direct connection to external PHY; supports 10/100 Mbps with IEEE 1588 timestamping capability. |
| FLEXCAN1_TX / RX | CAN bus differential signaling pair | Interface to CAN transceiver; supports ISO 11898-1 compliant communication up to 1 Mbps. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated DCDC + LDO power management | Reduces external power components by >50%; simplifies PCB layout and eliminates complex power sequencing. |
| FlexRAM configuration (32 KB granularity) | Enables runtime allocation of TCM vs OCRAM - critical for balancing cache latency and data buffer size in motor control algorithms. |
| Dual FlexPWM with fault protection | Supports 8 independent 16-bit PWM outputs with dead-time insertion and fault shutdown - suitable for 3-phase inverter gate drive. |
| BEE with AES-128 CTR mode | Enables transparent decryption of external QSPI flash at boot and runtime - secures firmware while maintaining XIP performance. |
| SAI modules with TDM support | Allows daisy-chained multi-microphone arrays or multi-speaker systems using single serial bus - reduces pin count and routing complexity. |
Applications
| Industrial Motor Control | Smart Home Appliance Hub |
|---|---|
Use Scenario: Closed-loop servo drive for BLDC/PMSM motors in HVAC compressors or washing machine drums. IC Role / Device Role / Timing Role: Real-time motion controller executing FOC algorithms at 500 MHz, coordinating PWM, ADC sampling, and encoder feedback via QuadTimer. Use Value: Integrated FlexPWM (8 channels), 2× Quad Timers with quadrature decode, and 2× 12-bit ADC enable precise torque/speed regulation without external timing ICs or gate drivers. |
Use Scenario: Central hub aggregating BLE/Wi-Fi sensors, managing appliance UI, and streaming audio to speakers. IC Role / Device Role / Timing Role: Application processor handling protocol stacks (BLE host, Wi-Fi offload), audio playback (SAI+SPDIF), and touch/keypad (KPP) with secure OTA update. Use Value: On-chip 4 MB flash stores full firmware + assets; dual uSDHC supports local media caching; HAB+DCP ensures signed firmware validation before execution. |
| IoT Edge Gateway | Human-Machine Interface (HMI) |
Use Scenario: Field-deployed gateway collecting Modbus/KNX data, performing local analytics, and forwarding to cloud via TLS-secured Ethernet. IC Role / Device Role / Timing Role: Secure network edge node with IEEE 1588 time synchronization, dual CAN for legacy fieldbus bridging, and hardware crypto acceleration. Use Value: 10/100 ENET with hardware timestamping enables sub-microsecond time alignment; DCP and SNVS provide TLS key generation and secure key storage. |
Use Scenario: Touch-enabled panel for factory floor equipment with audio alerts, status LEDs, and real-time diagnostics display. IC Role / Device Role / Timing Role: Graphics/audio co-processor driving LCD via SEMC and generating voice prompts via MQS or SAI. Use Value: SEMC supports parallel NOR/SDRAM for frame buffer; MQS delivers stereo audio over GPIOs - eliminating dedicated audio DAC and reducing BoM cost. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar crossover processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMXRT1021DAG5A | No on-chip flash (requires external QSPI); same 500 MHz M7 core, 256 KB RAM, and peripheral set except missing BEE and reduced security features. | Suitable for cost-sensitive designs where external flash is acceptable and cryptographic acceleration is not required. | Select MIMXRT1021DAG5A when flash density is secondary to BOM cost and security requirements are minimal. |
| MIMXRT1052DVL6B | 600 MHz M7 core, 512 KB RAM, 0 MB on-chip flash, 196-pin BGA package; adds LCDIF, MIPI-CSI, and enhanced crypto (CAAM). | Targeted at display-rich applications (e.g., smart displays) requiring higher compute throughput and camera interface - not pin-compatible. | Choose MIMXRT1052DVL6B only when display/camera integration and >500 MHz performance justify BGA packaging and external flash dependency. |
Compared with MIMXRT1024DAG5B, MIMXRT1021DAG5A removes flash and security accelerators to reduce cost, while MIMXRT1052DVL6B trades flash for higher clock speed and display peripherals in a larger BGA - neither is pin-compatible, but both serve adjacent segments in the i.MX RT family roadmap.
Availability
MIMXRT1024DAG5B is available at Aetrix Electronics and suitable for industrial motor control, smart home appliance hubs, and IoT edge gateways requiring stable component supply, long-term lifecycle assurance, and qualified production volumes.
Supply support for MIMXRT1024DAG5B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based microcontrollers and crossover processors.
The i.MX RT series - including the MIMXRT1024DAG5B - was designed to bridge the gap between MCUs and application processors, delivering MCU-level ease-of-use with application-processor-class performance for real-time edge intelligence.
FAQ
What is the maximum operating frequency of the MIMXRT1024DAG5B?
The MIMXRT1024DAG5B operates at a maximum core frequency of 500 MHz under consumer-grade temperature conditions (0 °C to +95 °C junction). This frequency is sustained across its full voltage range (0.9 V to 1.3 V VDD_SOC) and is validated per Table 11 in the IMXRT1024CEC datasheet Rev. 2.
Does the MIMXRT1024DAG5B include on-chip flash memory?
Yes, the MIMXRT1024DAG5B integrates 4 MB of on-chip flash memory, enabling XIP (execute-in-place) operation and eliminating the need for external flash in many embedded applications. This flash is managed by the Boot ROM and supports secure boot via High Assurance Boot (HAB).
How many GPIO pins does the MIMXRT1024DAG5B support in its 144-pin LQFP package?
The MIMXRT1024DAG5B provides 90 general-purpose I/O pins in its 144-pin LQFP package, as confirmed in Table 2 of the IMXRT1024CEC datasheet. These GPIOs are fully multiplexed via the IOMUXC and support interrupt capability, pull-up/down, and drive strength configuration.
What security features are implemented in the MIMXRT1024DAG5B?
The MIMXRT1024DAG5B includes hardware-accelerated security features: High Assurance Boot (HAB), Data Co-Processor (DCP) supporting AES-128 and SHA-256, Bus Encryption Engine (BEE) for on-the-fly QSPI decryption, Secure Non-Volatile Storage (SNVS) with secure RTC, and True Random Number Generation (TRNG).
Is the MIMXRT1024DAG5B pin-compatible with other i.MX RT102x variants?
No - the MIMXRT1024DAG5B shares the same 144-pin LQFP package footprint with MIMXRT1024DAG5A, but is not pin-compatible with other i.MX RT102x derivatives such as the RT1021 (same package but different peripheral mapping) or RT1020 (different feature set and pin assignment per Table 1).
MIMXRT1024DAG5B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 144-LQFP
- Series:
- RT1024
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M7
- Core Size:
- 32-Bit
- Speed:
- 500MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, POR, PWM, WDT
- Number of I/O:
- 90
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.15V ~ 1.3V
- Data Converters:
- A/D 19x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- 0°C ~ 95°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MIMXRT1024DAG5B FAQ
1.How can I place an order for MIMXRT1024DAG5B through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMXRT1024DAG5B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMXRT1024DAG5B reliable?
The price and inventory of MIMXRT1024DAG5B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMXRT1024DAG5B is usually 5 days.
3.What payment methods are accepted for MIMXRT1024DAG5B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIMXRT1024DAG5B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIMXRT1024DAG5B?
MIMXRT1024DAG5B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMXRT1024DAG5B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMXRT1024DAG5B?
For technical support, including MIMXRT1024DAG5B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMXRT1024DAG5B requirements.
6.How does Aetrix verify that MIMXRT1024DAG5B is sourced from the original manufacturer or authorized distributors?
All MIMXRT1024DAG5B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMXRT1024DAG5B meets industry standards.
7.What is the process for return or replacement of MIMXRT1024DAG5B?
All MIMXRT1024DAG5B units undergo pre-shipment inspection (PSI). If there is an issue with MIMXRT1024DAG5B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMXRT1024DAG5B part is unused and in its original packaging.
Return procedure for MIMXRT1024DAG5B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MIMXRT1024DAG5B Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
