NXP Semiconductors MIMXRT1061DVJ6B
- Part No.:
- MIMXRT1061DVJ6B
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 196-LFBGA
- Datasheet:
-
MIMXRT1061DVJ6B.pdf
- Description:
- IC MCU 32BIT EXT MEM 196LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,026
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MIMXRT1061DVJ6B from NXP Semiconductors is a 600 MHz Arm Cortex-M7 crossover processor with MPU/FPU, 1 MB on-chip RAM (512 KB TCM-configurable), dual FlexSPI interfaces, and integrated DCDC/LDO power management. It supports eMMC 4.5/SD 3.0, dual 10/100 Ethernet with IEEE 1588, two USB 2.0 OTG controllers, and real-time motor control via four FlexPWM modules. It targets industrial HMI and embedded edge applications requiring deterministic response and secure boot.
For engineers reviewing the MIMXRT1061DVJ6B datasheet, MIMXRT1061DVJ6B pinout, MIMXRT1061DVJ6B application, or MIMXRT1061DVJ6B equivalent, this page delivers verified specifications, package mapping, functional differentiation from RT1062 variants, and validated alternative options for cost-optimized or feature-extended designs.
Technical Context
The MIMXRT1061DVJ6B implements a single Arm Cortex-M7 core with 32 KB I-cache, 32 KB D-cache, VFPv5 FPU, and MPU supporting up to 16 protection regions. Its memory subsystem includes 128 KB boot ROM and flexible 1 MB OCRAM allocation across I-TCM/D-TCM/general-purpose RAM.
It integrates dual FlexSPI controllers for XIP-capable Quad SPI NOR/NAND, SEMC for SDRAM/NOR/PSRAM, two FlexCAN modules (one with CAN FD), and four quadrature encoder interfaces - all synchronized to a high-speed GPIO domain operating at core frequency.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M7 @ 600 MHz with FPU, MPU, 32 KB I/D cache |
| On-chip Memory | 1 MB OCRAM: 512 KB configurable as I-TCM/D-TCM, 512 KB general-purpose |
| Boot Source | 128 KB ROM with High Assurance Boot (HAB) and secure key provisioning |
| Power Management | Integrated DCDC (0.9–1.3 V output) and LDOs; eliminates external PMIC for most designs |
| Connectivity | Dual 10/100 Ethernet w/ IEEE 1588, two USB 2.0 OTG w/ PHY, eight UARTs, four I²C, four SPI |
| Security | HAB, DCP (AES-128/SHA-256/CRC-32), BEE (on-the-fly QSPI decryption), TRNG, SNVS w/ RTC |
| Analog Peripherals | Two 12-bit ADCs (16-channel each, 20-channel total), four ACMPs, touch sensing controller (TSC) |
Pinout & Package
196-pin MAPBGA, 10 × 10 mm body, 0.65 mm pitch - RoHS-compliant, lead-free, moisture-sensitive level 3 (MSL3).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Core logic supply | 1.0–1.3 V input to internal DCDC regulator; powers Cortex-M7, caches, TCM, and system logic |
| VDDA | Analog reference supply | 3.3 V analog rail for ADC, ACMP, and TSC; requires low-noise filtering per datasheet Section 4.8 |
| BOOT_MODE[1:0] | Boot configuration | Strapped at reset to select boot source: Quad SPI, SD/eMMC, USB MSD, or serial downloader |
| ENET_RXD0–3 / TXD0–3 | Ethernet physical interface | Dedicated RMII/MII pins for dual 10/100 Ethernet; supports IEEE 1588 timestamping in hardware |
| FLEXSPI_A_DATA0–3 / B_DATA0–3 | Quad SPI flash interface | Two independent FlexSPI controllers; each supports dual-channel XIP, octal mode, and on-the-fly BEE decryption |
Key Features
| Feature | Design Value |
|---|---|
| Secure Boot Architecture | HAB v4 with signed image validation, DCP-accelerated crypto, and immutable root-of-trust in boot ROM |
| Real-Time Motor Control | Four FlexPWM modules (8 channels total), four quadrature encoders, and GPT timers with sub-microsecond capture resolution |
| Low-Power System Integration | On-die DCDC + LDO reduces external component count; GPC hardware power controller enables dynamic voltage/frequency scaling |
| Audio Interface Flexibility | Three SAI modules support I²S/AC97/TDM; MQS generates stereo audio directly from GPIOs without codec |
| Memory Expansion Support | SEMC supports 8/16-bit SDRAM (up to 133 MHz), parallel NOR with XIP, NAND with software ECC, and PSRAM |
Applications
| Industrial HMI | Smart Home Gateway |
|---|---|
Use Scenario: Touch-enabled panel controlling HVAC, lighting, and security systems in residential buildings. IC Role / Device Role / Timing Role: Main application processor executing Linux/FreeRTOS UI stack, managing display refresh via GPIO-driven LCDIF, and handling sensor data aggregation. Use Value: Integrated DCDC and 127 GPIOs simplify board layout; dual Ethernet enables local LAN + cloud uplink with IEEE 1588 time sync for coordinated device actions. |
Use Scenario: Central hub aggregating Zigbee, Matter-over-Thread, and BLE devices while bridging to Wi-Fi or cellular backhaul. IC Role / Device Role / Timing Role: Secure host processor running Matter SDK, performing cryptographic offload via DCP/BEE, and managing concurrent protocol stacks. Use Value: HAB + SNVS ensures firmware integrity and secure key storage; FlexIO supports custom PHY bridging without FPGA; TRNG feeds entropy to TLS handshakes. |
| Motor Drive Controller | Edge-AI Sensor Node |
Use Scenario: Closed-loop servo drive for CNC axes using Hall-effect feedback and field-oriented control (FOC). IC Role / Device Role / Timing Role: Real-time motion controller executing FOC algorithm at 20 kHz PWM rate, sampling ADC at 1 MSPS, and updating PWM duty cycles within 100 ns jitter. Use Value: Tightly coupled GPIOs run at 600 MHz; four FlexPWM modules deliver synchronized 16-bit waveforms; quadrature encoders decode position with hardware interpolation. |
Use Scenario: Battery-powered vibration/temperature node performing local anomaly detection before wireless upload. IC Role / Device Role / Timing Role: Low-power edge AI accelerator running quantized neural network inference on ADC samples, using PXP for pre-processing and MQS for audible alerts. Use Value: 1 MB on-chip RAM stores model weights and buffers; LPSPI/LPI2C maintain sensor connectivity in stop mode; DCDC efficiency >85% extends battery life beyond 2 years. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar crossover processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMXRT1062DVJ6B | Includes LCDIF, CSI, and PXP graphics acceleration; same CPU, memory, and peripheral set otherwise | Required for RGB display or camera-based vision tasks; adds ~$0.80 BOM cost and 1.2 mm² PCB area | Select when display interface or pixel processing is mandatory; MIMXRT1061DVJ6B saves cost and layout space where those features are unused. |
| MIMXRT1052CVL5B | 528 MHz Cortex-M7, 512 KB SRAM (no TCM flexibility), no DCDC, single Ethernet, no CAN FD | Suitable for lower-cost HMI or gateway where 600 MHz headroom, dual Ethernet, or CAN FD are unnecessary | Choose for cost-sensitive volume production where full RT106x feature set is over-provisioned; verify thermal margin at 528 MHz under sustained load. |
Compared with MIMXRT1062DVJ6B, MIMXRT1061DVJ6B removes display/camera hardware to reduce cost and power; compared with MIMXRT1052CVL5B, it adds 72 MHz performance headroom, integrated DCDC, dual Ethernet, and CAN FD - enabling higher-fidelity real-time control and secure multi-network edge nodes.
Availability
MIMXRT1061DVJ6B is available at Aetrix Electronics and suitable for industrial HMI, motor control, and smart home gateway designs requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for MIMXRT1061DVJ6B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based microcontrollers and crossover processors.
The i.MX RT1060 family - including MIMXRT1061DVJ6B - was designed to bridge the gap between MCU simplicity and MPU performance, targeting real-time edge applications needing deterministic latency, rich peripherals, and hardware-enforced security.
FAQ
What is the maximum operating frequency of the MIMXRT1061DVJ6B?
The MIMXRT1061DVJ6B operates at a maximum core frequency of 600 MHz, as specified in Table 10 ("Operating ranges") of the IMXRT1060CEC datasheet Rev. 4. This frequency is guaranteed across the commercial temperature range (0°C to +95°C junction) with appropriate voltage regulation and thermal management. The MIMXRT1061DVJ6B achieves this using its integrated DCDC converter and optimized clock tree.
Does the MIMXRT1061DVJ6B include an integrated DCDC converter?
Yes, the MIMXRT1061DVJ6B integrates a programmable DCDC converter supporting 0.9–1.3 V output in run mode, eliminating the need for an external PMIC in most designs. This DCDC powers the SOC core logic (VDD_SOC) and is documented in Section 4.2 ("System power and clocks") of the IMXRT1060CEC datasheet. External filtering components are required per Figure 4-1.
How many ADC channels does the MIMXRT1061DVJ6B support?
The MIMXRT1061DVJ6B integrates two 12-bit Analog-to-Digital Converters (ADC1 and ADC2), each supporting 16 input channels, for a total of 20 unique analog inputs. This is confirmed in Table 2 ("i.MX RT1060 modules list") and Section 4.8 ("Analog") of the IMXRT1060CEC datasheet. Channel mapping and sampling rates are defined in the reference manual.
Is the MIMXRT1061DVJ6B pin-compatible with the MIMXRT1062DVJ6B?
No, the MIMXRT1061DVJ6B and MIMXRT1062DVJ6B share the same 196-pin MAPBGA package (10 × 10 mm, 0.65 mm pitch) and identical pinout per Section 6.1 of the IMXRT1060CEC datasheet, but they are not functionally identical: MIMXRT1062DVJ6B exposes LCDIF, CSI, and PXP signals on otherwise unused pins, while MIMXRT1061DVJ6B repurposes those balls for GPIO or leaves them NC. PCB layout must match the target variant's signal mapping.
What security features are implemented in hardware on the MIMXRT1061DVJ6B?
The MIMXRT1061DVJ6B implements hardware-accelerated security including High Assurance Boot (HAB), Data Co-Processor (DCP) for AES-128/SHA-256/CRC-32, Bus Encryption Engine (BEE) for on-the-fly QSPI decryption, True Random Number Generator (TRNG), and Secure Non-Volatile Storage (SNVS) with RTC. These are detailed in Sections 1.1 and 4.9 of the IMXRT1060CEC datasheet and require fuse programming for full enablement.
MIMXRT1061DVJ6B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 196-LFBGA
- Series:
- RT1060
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M7
- Core Size:
- 32-Bit Single-Core
- Speed:
- 600MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- -
- Program Memory Type:
- External Program Memory
- EEPROM Size:
- -
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 3.6V
- Data Converters:
- A/D 20x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- 0°C ~ 95°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MIMXRT1061DVJ6B FAQ
1.How can I place an order for MIMXRT1061DVJ6B through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMXRT1061DVJ6B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMXRT1061DVJ6B reliable?
The price and inventory of MIMXRT1061DVJ6B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMXRT1061DVJ6B is usually 5 days.
3.What payment methods are accepted for MIMXRT1061DVJ6B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIMXRT1061DVJ6B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIMXRT1061DVJ6B?
MIMXRT1061DVJ6B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMXRT1061DVJ6B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMXRT1061DVJ6B?
For technical support, including MIMXRT1061DVJ6B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMXRT1061DVJ6B requirements.
6.How does Aetrix verify that MIMXRT1061DVJ6B is sourced from the original manufacturer or authorized distributors?
All MIMXRT1061DVJ6B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMXRT1061DVJ6B meets industry standards.
7.What is the process for return or replacement of MIMXRT1061DVJ6B?
All MIMXRT1061DVJ6B units undergo pre-shipment inspection (PSI). If there is an issue with MIMXRT1061DVJ6B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMXRT1061DVJ6B part is unused and in its original packaging.
Return procedure for MIMXRT1061DVJ6B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MIMXRT1061DVJ6B Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

