NXP Semiconductors MIMXRT1062XVN5B
- Part No.:
- MIMXRT1062XVN5B
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 225-LFBGA
- Datasheet:
-
MIMXRT1062XVN5B.pdf
- Description:
- IC MCU 32BIT 128KB ROM 225MAPBGA
- Quantity:
- Payment:

- Shipping:

Inventory:397
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MIMXRT1062XVN5B from NXP Semiconductors is a 500 MHz Arm Cortex-M7 crossover processor with 1 MB on-chip RAM (512 KB TCM/OCRAM configurable), dual 10/100 Ethernet controllers with IEEE 1588 support, and integrated DCDC/LDO power management. It features LCD/CSI/PXP multimedia acceleration, three SAI audio interfaces, and hardware security including HAB, DCP (AES-128/SHA-256), BEE, and TRNG - deployed in industrial HMIs and motor control systems.
For engineers reviewing the MIMXRT1062XVN5B datasheet, MIMXRT1062XVN5B pinout, MIMXRT1062XVN5B application, or MIMXRT1062XVN5B equivalent, key selection criteria include confirmed LCDIF/CSI/PXP availability, dual FlexCAN (one with CAN FD), 149 GPIOs (146 tightly coupled), -40°C to +125°C junction rating, and 225-pin 13×13 mm 0.8 mm pitch BGA package compatibility.
Technical Context
The MIMXRT1062XVN5B implements a single Arm Cortex-M7 core with 32 KB I-cache, 32 KB D-cache, VFPv5 FPU, and MPU supporting 16 protection regions. Its memory subsystem includes 128 KB boot ROM, 1 MB on-chip RAM (512 KB OCRAM + 512 KB TCM-configurable), and SEMC/FlexSPI for external SDRAM, NOR/NAND, and Quad SPI flash.
Peripherals include dual 10/100 ENET with IEEE 1588 timestamping, LCDIF driving WXGA parallel RGB displays, CSI supporting 24-bit RGB888/YUV444 input, PXP for real-time pixel processing (rotation, CSC, alpha blending), and four FlexPWM modules (16-bit resolution, up to 8 channels each) for motor control timing precision.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M7 @ 500 MHz - deterministic real-time execution with FPU and MPU for safety-critical firmware. |
| On-chip RAM | 1 MB total: 512 KB OCRAM + 512 KB TCM-configurable - enables low-latency code/data placement for time-sensitive ISR and control loops. |
| Display Interface | LCDIF + CSI + PXP - supports WXGA parallel RGB display output and 24-bit camera sensor input with hardware-accelerated composition. |
| Ethernet | Dual 10/100 ENET with IEEE 1588 hardware timestamping - enables synchronized motion control and industrial time-sensitive networking. |
| Security | HAB, DCP (AES-128/SHA-256), BEE (on-the-fly QSPI decryption), TRNG, SNVS - meets secure boot and encrypted firmware update requirements. |
| Power Management | Integrated DCDC + LDO - eliminates need for external PMIC, simplifies power sequencing, and supports run/standby voltage scaling (0.9–1.3 V). |
| Temperature Range | -40°C to +125°C junction - qualified for extended industrial environments without derating. |
Pinout & Package
225-pin plastic BGA package, 13 × 13 mm body size, 0.8 mm ball pitch, RoHS-compliant. Ball map defined per Section 6.1.3 of i.MX RT1060X Data Sheet Rev. 1 (06/2022).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Core logic supply | 1.0–1.3 V regulated input for Cortex-M7 core and TCM; requires local decoupling per datasheet layout guidelines. |
| VDDA | Analog supply | 3.3 V analog rail for ADC, ACMP, and temperature sensor - must be filtered separately from digital supplies. |
| ENET1_RXD0–3 | Ethernet receive data | Differential pair inputs for 10/100 Mbps ENET1; require controlled impedance (50 Ω) routing and termination. |
| LCD_DATA0–23 | Parallel RGB data bus | 24-bit wide synchronous interface for WXGA display output; supports 8/16/24-bit color depth and index-color LUT. |
| CSI_DATA0–23 | Camera sensor data input | 24-bit parallel input supporting RGB888, YUV444, Bayer, and CCIR656 formats - routed with matched length for skew control. |
| FLEXCAN1_TX/RX | CAN 2.0B physical layer | Differential signaling pair for CAN FD-capable controller; requires 120 Ω termination at network ends. |
Key Features
| Feature | Design Value |
|---|---|
| Hardware-accelerated PXP engine | Real-time pixel processing at 1 pixel/clock - enables dynamic UI overlays, rotation, and color-space conversion without CPU load. |
| Dual FlexCAN with CAN FD support | One FlexCAN module compliant with ISO 11898-1:2015 CAN FD - allows 64-byte payloads at up to 8 Mbps for high-bandwidth vehicle diagnostics. |
| Integrated DCDC converter | Adjustable 0.9–1.3 V output with over-current/voltage protection - reduces external component count and improves power efficiency by >30% vs discrete solutions. |
| Secure boot via HAB v4 | Public-key authenticated boot flow with eFUSE-based root-of-trust - prevents unauthorized firmware execution and enforces cryptographic chain-of-trust. |
| Four FlexPWM modules | 16-bit resolution, up to 8 independent channels per module - delivers precise gate timing for 3-phase BLDC/PMSM motor drives with fault protection. |
Applications
| Industrial HMI | Motor Control Drive |
|---|---|
|
Use Scenario: Touch-enabled operator panel with real-time status visualization, multi-language UI, and Ethernet-based PLC integration. IC Role / Device Role / Timing Role: Main application processor executing FreeRTOS/Linux, driving parallel RGB LCD via LCDIF, capturing touch via TSC, and communicating via dual ENET. Use Value: PXP offloads UI rendering; dual ENET enables redundant control network; -40°C to +125°C rating ensures operation in factory-floor enclosures. |
Use Scenario: Closed-loop servo drive for CNC machinery requiring precise PWM timing, encoder feedback, and fieldbus connectivity. IC Role / Device Role / Timing Role: Real-time motion controller running deterministic control loop at 20 kHz, reading quadrature encoders via ENC modules, generating gate signals via FlexPWM. Use Value: 500 MHz Cortex-M7 with TCM provides sub-μs interrupt latency; hardware PWM dead-time insertion prevents shoot-through; CAN FD enables fast parameter upload. |
| Smart Home Gateway | Medical Imaging Edge Node |
|
Use Scenario: Central hub aggregating Zigbee/Z-Wave sensors, streaming video from IP cameras, and managing local automation rules. IC Role / Device Role / Timing Role: Application host running Linux, interfacing to uSDHC for local storage, USB OTG for peripheral attachment, and SAI for audio alert synthesis. Use Value: Dual uSDHC supports SDXC/HS200 for 200 MB/s video buffering; MQS generates audible alerts via GPIO; hardware crypto accelerates TLS handshakes. |
Use Scenario: Portable ultrasound device capturing real-time B-mode image data from analog front-end and displaying processed frames on embedded LCD. IC Role / Device Role / Timing Role: Image acquisition and preprocessing unit using CSI to ingest raw sensor data, PXP for real-time scan-conversion and contrast enhancement, LCDIF for display output. Use Value: CSI supports 24-bit Bayer input at >30 fps; PXP performs pixel-level CSC and gamma correction in hardware; 1 MB RAM buffers multiple frames without DRAM latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar crossover processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMXRT1064XVK5A | 600 MHz Cortex-M7, 2 MB on-chip RAM, no DCDC (requires external PMIC), same 225-pin BGA package. | Higher performance for AI inference or complex GUI; lacks integrated DCDC - increases BOM cost and layout complexity. | Select when >500 MHz clock speed or >1 MB RAM is required; verify thermal design for 600 MHz operation. |
| MIMXRT1052CVL5B | 500 MHz Cortex-M7, 512 KB RAM, no LCDIF/CSI/PXP, no dual ENET, 196-pin BGA (14×14 mm, 0.8 mm pitch). | Cost-optimized for non-display applications like smart meters or gateway control; lacks multimedia and industrial networking peripherals. | Select for non-graphical, non-camera, non-Ethernet applications where footprint and cost are primary constraints. |
Compared with MIMXRT1062XVN5B, MIMXRT1064XVK5A offers higher CPU throughput and memory but requires external power regulation, while MIMXRT1052CVL5B reduces cost and size at the expense of display, camera, and dual Ethernet capabilities - making MIMXRT1062XVN5B the optimal balance for integrated HMI+control designs.
Availability
MIMXRT1062XVN5B is available at Aetrix Electronics and suitable for industrial HMI, motor control drives, and smart home gateways requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for MIMXRT1062XVN5B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with R&D centers across Europe, Asia, and North America.
The i.MX RT1060X series targets high-performance, real-time edge applications demanding MCU-level determinism with MPU-level peripherals - bridging the gap between traditional microcontrollers and application processors.
FAQ
What is the maximum operating frequency of the MIMXRT1062XVN5B?
The MIMXRT1062XVN5B operates at a maximum frequency of 500 MHz. This is a fixed specification for this part number, as confirmed in Table 1 of the i.MX RT1060X Data Sheet Rev. 1. The 500 MHz speed applies across the full -40°C to +125°C junction temperature range without derating. Higher-frequency variants such as the MIMXRT1064XVK5A run at 600 MHz but are not pin-compatible with the MIMXRT1062XVN5B.
Does the MIMXRT1062XVN5B include integrated DCDC and LDO regulators?
Yes, the MIMXRT1062XVN5B integrates both a DCDC converter and LDO regulators as part of its advanced power management unit. The DCDC supports 0.9–1.3 V output for core logic, while the LDO supplies I/O and analog domains. This integration eliminates the need for external PMICs and simplifies power sequencing - a confirmed feature listed in Table 1 under "Features" for MIMXRT1062XVN5B.
Which display and camera interfaces are supported by the MIMXRT1062XVN5B?
The MIMXRT1062XVN5B supports LCDIF for parallel RGB displays up to WXGA resolution, CSI for 24-bit parallel camera sensor input (RGB888/YUV444/Bayer), and PXP for hardware-accelerated pixel processing. These interfaces are explicitly enabled in the MIMXRT1062XVN5B feature set per Table 1, distinguishing it from the MIMXRT1061XVN5B which omits LCD/CSI/PXP.
How many Ethernet controllers does the MIMXRT1062XVN5B integrate, and do they support IEEE 1588?
The MIMXRT1062XVN5B integrates two 10/100 Mbps Ethernet controllers (ENET), both with full hardware support for IEEE 1588 Precision Time Protocol timestamping. This capability is documented in Section 4.9.4 and Table 1 of the i.MX RT1060X Data Sheet, enabling synchronized motion control and time-critical industrial networking without external PHY timestamping logic.
Is the MIMXRT1062XVN5B pin-compatible with other i.MX RT1060X family members?
The MIMXRT1062XVN5B uses a 225-pin 13×13 mm 0.8 mm pitch BGA package, matching the MIMXRT1061XVN5B and MIMXRT1064XVK5A. However, pin compatibility is not guaranteed across all signals due to functional differences - for example, LCDIF and CSI pins present on MIMXRT1062XVN5B are NC on MIMXRT1061XVN5B. Always verify ball mapping in Section 6.1.3 before PCB reuse.
MIMXRT1062XVN5B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 225-LFBGA
- Series:
- RT1060
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M7
- Core Size:
- 32-Bit
- Speed:
- 500MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
- Number of I/O:
- 149
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- ROM
- EEPROM Size:
- -
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 3.6V
- Data Converters:
- A/D 20x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MIMXRT1062XVN5B FAQ
1.How can I place an order for MIMXRT1062XVN5B through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMXRT1062XVN5B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMXRT1062XVN5B reliable?
The price and inventory of MIMXRT1062XVN5B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMXRT1062XVN5B is usually 5 days.
3.What payment methods are accepted for MIMXRT1062XVN5B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIMXRT1062XVN5B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIMXRT1062XVN5B?
MIMXRT1062XVN5B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMXRT1062XVN5B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMXRT1062XVN5B?
For technical support, including MIMXRT1062XVN5B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMXRT1062XVN5B requirements.
6.How does Aetrix verify that MIMXRT1062XVN5B is sourced from the original manufacturer or authorized distributors?
All MIMXRT1062XVN5B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMXRT1062XVN5B meets industry standards.
7.What is the process for return or replacement of MIMXRT1062XVN5B?
All MIMXRT1062XVN5B units undergo pre-shipment inspection (PSI). If there is an issue with MIMXRT1062XVN5B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMXRT1062XVN5B part is unused and in its original packaging.
Return procedure for MIMXRT1062XVN5B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MIMXRT1062XVN5B Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

