NXP Semiconductors MIMXRT106FCVL5B
- Part No.:
- MIMXRT106FCVL5B
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 196-LFBGA
- Datasheet:
-
MIMXRT106FCVL5B.pdf
- Description:
- IC MCU 32BIT 128KB ROM 196MAPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
MIMXRT106FCVL5B from NXP Semiconductors is an industrial-grade Arm Cortex-M7 crossover processor operating at 528 MHz, featuring 1 MB on-chip RAM (512 KB OCRAM + 512 KB TCM), integrated DCDC/LDO power management, and hardware-accelerated security (HAB/DCP/BEE/TRNG/SNVS). It supports face and emotion recognition turnkey solutions and targets HMI, industrial vision, and edge AI inference in harsh environments.
For engineers reviewing the MIMXRT106FCVL5B datasheet, MIMXRT106FCVL5B pinout, MIMXRT106FCVL5B application, or MIMXRT106FCVL5B equivalent, key selection criteria include its 196-pin MAPBGA-10×10 mm package, -40°C to +105°C junction temperature rating, dual FlexSPI with XIP support, parallel CSI for camera input, and PXP 2D graphics engine for real-time image preprocessing.
Technical Context
The MIMXRT106FCVL5B implements a single Arm Cortex-M7 core with 32 KB I-cache, 32 KB D-cache, and full VFPv5 FPU, tightly coupled to 512 KB of configurable TCM memory for deterministic real-time execution. Its memory subsystem includes boot ROM (128 KB), SEMC for external SDRAM/NAND/NOR, and dual FlexSPI controllers supporting octal flash and on-the-fly decryption.
Peripherals are organized around high-bandwidth interconnects: four FlexPWM modules (16-bit resolution, up to 8 channels total) for motor control, four Quad Timers with quadrature decoding, parallel CSI (24-bit RGB/YUV/Bayer), LCDIF with WXGA support, and three SAI interfaces for multi-channel audio I/O - all enabled in this industrial variant per Table 1.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M7 @ 528 MHz - delivers deterministic real-time response with FPU and MPU for safety-critical industrial code. |
| On-chip Memory | 1 MB RAM (512 KB OCRAM + 512 KB TCM) - enables zero-wait-state code execution and large frame buffers for vision processing. |
| Package | 196-pin MAPBGA, 10 × 10 mm, 0.65 mm pitch - compact industrial footprint with thermal performance validated for -40°C to +105°C operation. |
| Temperature Grade | Industrial (-40°C to +105°C) - qualified for deployment in factory automation, outdoor kiosks, and embedded vision systems without derating. |
| Security | HAB v4, DCP (AES-128/SHA-256), BEE (on-the-fly QSPI decryption), TRNG, SNVS - enables secure boot, encrypted firmware updates, and protected key storage. |
| Camera Interface | Parallel CSI (24-bit RGB/YUV/Bayer) - supports direct connection to CMOS image sensors for face/emotion recognition pipelines. |
| Graphics Acceleration | PXP pixel pipeline - performs real-time color-space conversion, alpha blending, rotation, and resize without CPU load. |
Pinout & Package
196-pin MAPBGA, 10 × 10 mm, 0.65 mm pitch package with exposed thermal pad; pin assignments follow i.MX RT1060 reference design layout (Document IMXRT1060IEC Rev. 4, Sections 6.1 and A.1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Core Power Supply | 1.0–1.3 V supply for Cortex-M7 core and TCM; requires tight regulation and local decoupling per Section 4.2. |
| VDDA | Analog Power Supply | 3.3 V analog domain supply for ADC, ACMP, and TSC; must be isolated from digital noise sources. |
| CSI_DATA0–23 | Parallel Camera Data Bus | 24-bit bidirectional data lines for synchronous camera sensor interface; routed with matched length and controlled impedance. |
| FLEXSPI_A_DATA0–7 | Quad SPI Flash Data | Dual 8-bit data bus for high-speed XIP-capable flash; supports on-the-fly BEE decryption for secure boot. |
| ENET_RXD0–3 / TXD0–3 | Ethernet PHY Interface | 10/100 Mbps RMII/MII signals with IEEE 1588 timestamping capability for synchronized industrial networking. |
Key Features
| Feature | Design Value |
|---|---|
| Face Recognition Turnkey Solution | Pre-integrated software stack and hardware acceleration (PXP + CSI + DCP) optimized for NXP's MCU-Vision2 platform targeting low-latency facial analysis. |
| Integrated Power Management | On-die DCDC converter (0.9–1.3 V output) and LDOs eliminate need for external PMIC, reducing BOM count and simplifying power sequencing. |
| Real-Time Vision Pipeline | Parallel CSI + PXP + eDMA enable zero-copy image capture, preprocessing (resize/CSC/rotation), and buffer transfer to OCRAM for neural network inference. |
| Secure Edge Deployment | HAB v4 + SNVS RTC + TRNG + BEE allows cryptographically verified boot, tamper-resistant timekeeping, and encrypted firmware storage in external QSPI. |
| Industrial Connectivity Suite | Dual 10/100 Ethernet with IEEE 1588, eight UARTs, four I²C, four SPI, two FlexCAN FD, and USB OTG - supports multi-protocol industrial gateways. |
Applications
| Industrial HMI with Face Authentication | Smart Factory Camera Node |
|---|---|
Use Scenario: Touchless access control terminal in manufacturing plant requiring user identification before machine startup. IC Role / Device Role / Timing Role: MIMXRT106FCVL5B acts as vision processor and system controller - captures live video via CSI, runs face detection on PXP-optimized pipeline, validates identity using DCP-secured model, and asserts safety interlock signals. Use Value: Eliminates physical credential readers; leverages on-chip TCM for sub-100 ms inference latency and SNVS for secure credential storage across power cycles. | Use Scenario: Embedded vision node monitoring conveyor belt for defect detection and part classification. IC Role / Device Role / Timing Role: MIMXRT106FCVL5B serves as standalone vision SoC - acquires images via parallel CSI, preprocesses frames using PXP, executes lightweight CNN on OCRAM-resident weights, and reports results over Ethernet. Use Value: Avoids external FPGA or GPU; achieves 30 FPS at VGA resolution using only on-chip resources and industrial-grade thermal reliability. |
| Edge AI Gateway for Building Automation | Robotic Vision Controller |
Use Scenario: On-premise gateway aggregating data from multiple cameras and environmental sensors in smart buildings. IC Role / Device Role / Timing Role: MIMXRT106FCVL5B functions as central edge AI hub - ingests video streams via CSI, processes metadata with DCP-accelerated encryption, and forwards alerts via dual Ethernet with IEEE 1588 time synchronization. Use Value: Single-chip solution replaces multi-chip designs; industrial temp grade ensures stable operation in unconditioned mechanical rooms. | Use Scenario: Real-time vision feedback loop for collaborative robot performing precision assembly with human proximity detection. IC Role / Device Role / Timing Role: MIMXRT106FCVL5B operates as low-latency vision coprocessor - captures stereo camera input, computes depth maps via PXP-accelerated algorithms, and feeds position data to motion controller over FlexPWM-triggered GPIO. Use Value: Sub-millisecond end-to-end latency from image capture to actuator command; deterministic timing ensured by TCM-resident code and GPT-synchronized triggers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar crossover processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMXRT1062CVL5B | Same core, package, and memory; lacks face recognition turnkey software stack and pre-validated vision pipeline optimizations. | Suitable for general-purpose industrial HMI but requires custom vision framework integration. | Select MIMXRT1062CVL5B when full flexibility in algorithm choice outweighs need for pre-validated face recognition deployment. |
| MIMXRT106ACVL5B | Identical hardware spec; optimized for far-field audio front-end (AVS) instead of vision - different firmware SDK and peripheral tuning. | Targeted at voice-controlled devices; CSI/PXP features present but not software-validated for vision workloads. | Choose MIMXRT106ACVL5B only if audio processing dominates system requirements and vision is secondary or absent. |
Compared with MIMXRT1062CVL5B and MIMXRT106ACVL5B, the MIMXRT106FCVL5B uniquely integrates factory-tuned vision firmware, PXP-optimized face detection kernels, and BEE-decrypted QSPI boot - enabling faster time-to-market for industrial biometric applications without compromising industrial temperature qualification or security certification paths.
Availability
MIMXRT106FCVL5B is available at Aetrix Electronics and suitable for industrial HMI, edge AI vision nodes, robotic controllers, and building automation gateways requiring stable component supply across extended product lifecycles.
Supply support for MIMXRT106FCVL5B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The i.MX RT1060 family - including MIMXRT106FCVL5B - was designed as a crossover processor line bridging MCU simplicity with MPU-level performance, specifically targeting real-time industrial vision, voice, and HMI applications with integrated security and power efficiency.
FAQ
What is the maximum operating frequency of the MIMXRT106FCVL5B?
The MIMXRT106FCVL5B operates at a maximum core frequency of 528 MHz, as specified in the i.MX RT1060 data sheet (IMXRT1060IEC Rev. 4, Section 1.1). This frequency is guaranteed across the full industrial temperature range (-40°C to +105°C) and supported by the on-chip PLL and voltage regulation circuitry. The MIMXRT106FCVL5B achieves this speed while maintaining deterministic real-time behavior through its tightly coupled memory architecture and cache configuration.
Does the MIMXRT106FCVL5B support secure boot and firmware encryption?
Yes, the MIMXRT106FCVL5B supports High Assurance Boot (HAB v4), Data Co-Processor (DCP) for AES-128/SHA-256, and Bus Encryption Engine (BEE) for on-the-fly QSPI flash decryption. These features are silicon-verified and enabled in the industrial-grade MIMXRT106FCVL5B variant per Table 1 of the IMXRT1060IEC data sheet. Secure boot validation occurs during reset, and BEE decryption is transparent to software execution.
What camera interfaces does the MIMXRT106FCVL5B support for face recognition applications?
The MIMXRT106FCVL5B supports a 24-bit parallel CSI interface compatible with RGB888, YUV444, Bayer, and CCIR656 formats - directly enabling connection to common CMOS image sensors used in face recognition systems. This interface is paired with the Pixel Processing Pipeline (PXP) for real-time preprocessing (resize, CSC, rotation), and the eDMA engine for zero-copy frame transfers into OCRAM - all confirmed for the MIMXRT106FCVL5B in Table 1 and Section 3.1 of IMXRT1060IEC.
Is the MIMXRT106FCVL5B pin-compatible with other i.MX RT106x variants in the same package?
Yes, the MIMXRT106FCVL5B uses the identical 196-pin MAPBGA, 10 × 10 mm, 0.65 mm pitch package and shares the same pinout as other VL-suffixed i.MX RT106x parts (e.g., MIMXRT1061CVL5B, MIMXRT1062CVL5B, MIMXRT106ACVL5B). Pin assignments are defined in Section 6.1 of IMXRT1060IEC Rev. 4 and validated across all VL-package derivatives - enabling hardware reuse across vision, audio, and general-purpose variants.
What development tools and software support are available for the MIMXRT106FCVL5B?
NXP provides MCUXpresso SDK, IDE, and Config Tools for the MIMXRT106FCVL5B, including pre-validated face recognition middleware under the MCU-Vision2 platform (nxp.com/mcu-vision2). The SDK includes drivers for CSI, PXP, DCP, and BEE, along with FreeRTOS and bare-metal examples. Hardware evaluation is supported by the MIMXRT1060-EVK board, which is compatible with the MIMXRT106FCVL5B's electrical and pinout specifications.
MIMXRT106FCVL5B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 196-LFBGA
- Series:
- RT1060
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M7
- Core Size:
- 32-Bit Single-Core
- Speed:
- 528MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- -
- Program Memory Type:
- External Program Memory
- EEPROM Size:
- -
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 3.6V
- Data Converters:
- A/D 20x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MIMXRT106FCVL5B FAQ
1.How can I place an order for MIMXRT106FCVL5B through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMXRT106FCVL5B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMXRT106FCVL5B reliable?
The price and inventory of MIMXRT106FCVL5B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMXRT106FCVL5B is usually 5 days.
3.What payment methods are accepted for MIMXRT106FCVL5B?
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4.How is shipping managed for MIMXRT106FCVL5B?
MIMXRT106FCVL5B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMXRT106FCVL5B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMXRT106FCVL5B?
For technical support, including MIMXRT106FCVL5B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMXRT106FCVL5B requirements.
6.How does Aetrix verify that MIMXRT106FCVL5B is sourced from the original manufacturer or authorized distributors?
All MIMXRT106FCVL5B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMXRT106FCVL5B meets industry standards.
7.What is the process for return or replacement of MIMXRT106FCVL5B?
All MIMXRT106FCVL5B units undergo pre-shipment inspection (PSI). If there is an issue with MIMXRT106FCVL5B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMXRT106FCVL5B part is unused and in its original packaging.
Return procedure for MIMXRT106FCVL5B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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