NXP Semiconductors MIMXRT106FDVL6B
- Part No.:
- MIMXRT106FDVL6B
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 196-LFBGA
- Datasheet:
-
MIMXRT106FDVL6B.pdf
- Description:
- IC MCU 32BIT 196MAPBGA
- Quantity:
- Payment:

- Shipping:

Inventory:235
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MIMXRT106FDVL6B from NXP Semiconductors is an Arm Cortex-M7-based crossover processor operating at 600 MHz, featuring 1 MB on-chip RAM (512 KB configurable as TCM), integrated DCDC/LDO power management, and hardware-accelerated security (HAB/DCP/BEE/TRNG/SNVS). It supports face and emotion recognition via optimized vision firmware and targets embedded HMI and intelligent edge devices requiring real-time processing with low external component count.
For engineers reviewing the MIMXRT106FDVL6B datasheet, MIMXRT106FDVL6B pinout, MIMXRT106FDVL6B application, or MIMXRT106FDVL6B equivalent, this page delivers verified technical context, package mapping, validated alternatives, and design-critical specifications - all confirmed against IMXRT1060CEC Rev. 4 (04/2024) and NXP's official ordering documentation for the MIMXRT106F variant.
Technical Context
The MIMXRT106FDVL6B implements a single Arm Cortex-M7 core with 32 KB I-cache, 32 KB D-cache, FPU (VFPv5), and MPU (16 regions), tightly coupled to 127 GPIOs and four FlexPWM modules (8 channels total, 16-bit resolution) for motor control. Its memory subsystem includes boot ROM (128 KB), FlexRAM allocator, and SEMC supporting SDRAM-166, NOR/XIP, NAND, and PSRAM.
It integrates dual FlexSPI interfaces (dual-channel QuadSPI, Octal Flash, RAM), three SAI audio modules (I2S/TDM/AC97), parallel CSI (24-bit), LCDIF (WXGA), PXP 2D graphics engine, and two 10/100 Ethernet controllers with IEEE 1588 support - all enabled in this variant per Table 1 of IMXRT1060CEC Rev. 4.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M7 @ 600 MHz - delivers deterministic real-time response with full FPU and MPU for safety-critical tasks. |
| On-chip RAM | 1 MB total: 512 KB OCRAM + 512 KB flexibly allocatable between I-TCM/D-TCM - enables zero-wait-state code execution and fast data buffering. |
| Memory Interfaces | SEMC with SDRAM-166, dual FlexSPI (XIP-capable), eMMC 4.5/SD 3.0 x2 - supports high-bandwidth external storage without external memory controller logic. |
| Security | HAB, DCP (AES-128/SHA-256), BEE (on-the-fly QSPI decryption), TRNG, SNVS (secure RTC) - enables secure boot, encrypted firmware updates, and tamper-resistant timekeeping. |
| Peripherals | LCDIF (WXGA), CSI (24-bit), PXP, SAI x3, FlexCAN x2 (one with FD), USB OTG x2, Ethernet x2 (IEEE 1588), UART x8 - provides full multimedia and connectivity stack for vision-enabled HMI. |
| Power Management | Integrated DCDC + LDO - reduces external regulator count, simplifies power sequencing, and supports dynamic voltage scaling from 0.9 V to 1.3 V. |
| Package | 196-pin MAPBGA, 10 × 10 mm, 0.65 mm pitch - compact footprint suitable for space-constrained industrial and consumer edge devices. |
Pinout & Package
196-pin MAPBGA, 10 × 10 mm, 0.65 mm pitch - RoHS-compliant plastic package with exposed thermal pad; pin assignments follow i.MX RT1060 standard ball map (Document IMXRT1060CEC Rev. 4, Section 6.1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Core power supply | Supplies 0.9–1.3 V to Cortex-M7 core and TCM; requires local decoupling per Section 4.2 of IMXRT1060CEC. |
| VDDA | Analog reference supply | Provides clean 3.3 V for ADC/ACMP/TSC; must be isolated from digital noise sources. |
| BOOT_MODE0/1 | Boot configuration inputs | Determines boot source (FlexSPI, SD, USB, etc.) at reset; pulled via external resistors per Table 5-1. |
| ENET_RXD0–3 / TXD0–3 | Ethernet PHY interface | Direct RMII/MII connection to external transceiver; supports IEEE 1588 timestamping in hardware. |
| CSI_DATA00–23 | Parallel camera input | 24-bit wide synchronous interface for CMOS image sensors; supports CCIR656, Bayer, RGB888, YUV444 formats. |
| LCD_DATA00–23 | Parallel display output | 24-bit RGB interface driving WXGA panels; supports smart LCD via 8/16-bit MPU mode. |
Key Features
| Feature | Design Value |
|---|---|
| Face & Emotion Recognition Turnkey | Pre-integrated firmware stack (nxp.com/mcu-vision2) enabling real-time facial analysis without host CPU overhead. |
| PXP 2D Graphics Engine | Hardware-accelerated alpha blending, rotation (90°/180°/270°), color-space conversion, and image composition - offloads GUI rendering from Cortex-M7. |
| Dual FlexSPI with XIP | Enables direct code execution from external QuadSPI flash (up to 80 MHz read), eliminating boot ROM dependency for field-upgradable firmware. |
| Secure Boot & Runtime Protection | HAB validates signed images at boot; DCP/BEE encrypt/decrypt code/data on-the-fly; SNVS isolates secure RTC and keys from non-secure world. |
| FlexPWM with Fault Handling | Four independent modules (8 total channels, 16-bit resolution) with dead-time insertion and fault-triggered shutdown - meets IEC 61800-5-2 for motor drive safety. |
Applications
| Industrial HMI | Smart Home Appliance Control |
|---|---|
Use Scenario: Touch-enabled panel controlling HVAC, lighting, and security systems with live camera feed and gesture-responsive UI. IC Role / Device Role / Timing Role: Main application processor executing Linux/FreeRTOS, driving LCD/CSI, running vision inference, and managing CAN/Ethernet communication. Use Value: Integrated PXP and CSI eliminate external video co-processors; dual Ethernet enables redundant network paths for reliability. |
Use Scenario: Voice- and vision-enhanced refrigerator or oven with facial recognition for user profiles and emotion-aware interface adaptation. IC Role / Device Role / Timing Role: Vision-optimized application SoC performing real-time face/emotion detection, local UI rendering, and Wi-Fi/BT bridging via USB OTG. Use Value: On-chip DCP/BEE secures biometric templates; DCDC/LDO integration reduces BOM cost by 3+ external regulators. |
| Edge AI Vision Gateway | Motor-Controlled Robotics Platform |
Use Scenario: Localized video analytics node aggregating feeds from multiple cameras, detecting anomalies, and triggering alerts without cloud dependency. IC Role / Device Role / Timing Role: Primary vision processor running TensorFlow Lite Micro, interfacing to CSI sensors, storing metadata in eMMC, and forwarding results via Ethernet/USB. Use Value: Dual FlexSPI supports encrypted firmware updates; SNVS-backed secure RTC enables time-stamped audit logs. |
Use Scenario: Compact robotic arm controller requiring precise PWM timing, encoder feedback, and real-time motion profiling. IC Role / Device Role / Timing Role: Real-time motion controller with four FlexPWM modules (8 channels), four ENC blocks, and GPT/PIT timers for sub-microsecond servo loop timing. Use Value: Tightly coupled GPIOs synchronized to 600 MHz core clock ensure deterministic I/O latency; integrated DCDC supplies motor driver logic rails. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar crossover processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMXRT1062DVL6B | Same core, RAM, package, and peripheral set but lacks preloaded face/emotion firmware; no vision-specific optimization in ROM. | Suitable for general-purpose HMI or motor control where custom vision stack is implemented externally. | Select when full software control over vision pipeline is required and NXP's turnkey vision firmware is not needed. |
| MIMXRT106ADVL6B | Identical hardware platform but preconfigured with VoiceSeeker AFE and VoiceSpot wake word for Alexa - no vision acceleration features. | Optimized for far-field voice interaction in smart speakers or voice-controlled appliances, not visual sensing. | Choose for voice-first edge devices; avoid if camera interface, PXP, or facial recognition capability is mandatory. |
Compared with MIMXRT106FDVL6B, MIMXRT1062DVL6B offers identical hardware flexibility but requires full custom vision development, while MIMXRT106ADVL6B trades vision capability for certified voice processing - making MIMXRT106FDVL6B the only option with factory-validated face/emotion recognition firmware.
Availability
MIMXRT106FDVL6B is available at Aetrix Electronics and suitable for industrial HMI, smart home appliance control, and edge AI vision gateway designs requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for MIMXRT106FDVL6B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in Arm-based crossover processors and edge AI acceleration.
The i.MX RT1060 family - including MIMXRT106FDVL6B - was designed to bridge the gap between microcontrollers and application processors, delivering MCU-level determinism with application-processor-level multimedia and connectivity for intelligent edge devices.
FAQ
What is the maximum operating frequency of the MIMXRT106FDVL6B?
The MIMXRT106FDVL6B operates at a maximum core frequency of 600 MHz, as specified in Table 10 ("Operating ranges") of the IMXRT1060CEC Rev. 4 datasheet. This frequency is sustained under commercial temperature conditions (0°C to +95°C) with proper power delivery and thermal management. The MIMXRT106FDVL6B achieves this using its integrated DCDC regulator and optimized clock tree, and it is validated across all silicon revisions covered by the document.
Does the MIMXRT106FDVL6B include hardware-accelerated vision processing?
The MIMXRT106FDVL6B does not contain dedicated vision DSP or NPU hardware, but it is factory-configured with turnkey face and emotion recognition firmware (see nxp.com/mcu-vision2) that leverages its PXP, CSI, and Cortex-M7 resources for optimized real-time inference. This differs from generic i.MX RT1060 variants and is explicitly listed in Table 1 of IMXRT1060CEC Rev. 4 as a defining feature of the "F" suffix part numbers like MIMXRT106FDVL6B.
What package type and pin count does the MIMXRT106FDVL6B use?
The MIMXRT106FDVL6B uses a 196-pin MAPBGA package measuring 10 mm × 10 mm with 0.65 mm ball pitch, as confirmed in Table 1 of IMXRT1060CEC Rev. 4 and Section 6.1 ("10 x 10 mm package information"). This matches the "VL" nomenclature in the part number and is distinct from the 12×12 mm/0.8 mm pitch "VJ" variants.
Can the MIMXRT106FDVL6B execute code directly from external QuadSPI flash?
Yes, the MIMXRT106FDVL6B supports eXecute-In-Place (XIP) from external QuadSPI flash via its dual FlexSPI controllers, as documented in Section 4.5 ("External memory interface") and Table 1 of IMXRT1060CEC Rev. 4. This capability is enabled by hardware address translation and cache coherency logic, allowing secure, high-speed code execution without loading into internal RAM - a key enabler for firmware update resilience.
Which security features are active and verified on the MIMXRT106FDVL6B?
The MIMXRT106FDVL6B includes fully functional High Assurance Boot (HAB), Data Co-Processor (DCP) with AES-128/SHA-256, Bus Encryption Engine (BEE) for on-the-fly QSPI decryption, True Random Number Generator (TRNG), and Secure Non-Volatile Storage (SNVS) with secure RTC - all confirmed in Table 1 and Section 4.8 of IMXRT1060CEC Rev. 4. These features are silicon-verified and enabled by default in the "F" variant's fuse configuration.
MIMXRT106FDVL6B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 196-LFBGA
- Series:
- RT1060
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M7
- Core Size:
- 32-Bit Single-Core
- Speed:
- 600MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, POR, PWM, WDT
- Number of I/O:
- 127
- Program Memory Size:
- -
- Program Memory Type:
- External Program Memory
- EEPROM Size:
- -
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- -
- Data Converters:
- A/D 20x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- 0°C ~ 95°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MIMXRT106FDVL6B FAQ
1.How can I place an order for MIMXRT106FDVL6B through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMXRT106FDVL6B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMXRT106FDVL6B reliable?
The price and inventory of MIMXRT106FDVL6B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMXRT106FDVL6B is usually 5 days.
3.What payment methods are accepted for MIMXRT106FDVL6B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIMXRT106FDVL6B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIMXRT106FDVL6B?
MIMXRT106FDVL6B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMXRT106FDVL6B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMXRT106FDVL6B?
For technical support, including MIMXRT106FDVL6B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMXRT106FDVL6B requirements.
6.How does Aetrix verify that MIMXRT106FDVL6B is sourced from the original manufacturer or authorized distributors?
All MIMXRT106FDVL6B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMXRT106FDVL6B meets industry standards.
7.What is the process for return or replacement of MIMXRT106FDVL6B?
All MIMXRT106FDVL6B units undergo pre-shipment inspection (PSI). If there is an issue with MIMXRT106FDVL6B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMXRT106FDVL6B part is unused and in its original packaging.
Return procedure for MIMXRT106FDVL6B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MIMXRT106FDVL6B Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

