NXP Semiconductors MIMXRT1172AVM8A
- Part No.:
- MIMXRT1172AVM8A
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 289-LFBGA
- Datasheet:
-
MIMXRT1172AVM8A.pdf
- Description:
- IC MCU 32BIT EXT MEM 289MAPBGA
- Quantity:
- Payment:

- Shipping:

Inventory:146
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MIMXRT1172AVM8A from NXP is a dual-core Arm® Cortex®-M7 (1 GHz) + Cortex®-M4 (400 MHz) crossover MCU with 2 MB total on-chip SRAM (512 KB M7 TCM + 256 KB M4 TCM + 1 MB RAM), hardware AES-128/256 encryption, and support for HyperFlash™/HyperRAM™, SDRAM, and eMMC/SD. It targets real-time industrial HMI and ML edge inference.
For engineers reviewing the MIMXRT1172AVM8A datasheet, MIMXRT1172AVM8A pinout, MIMXRT1172AVM8A application, or MIMXRT1172AVM8A equivalent, key selection criteria include dual-core clock speeds, ECC-configurable SRAM partitioning, MIPI DSI/CSI interface availability, Ethernet TSN support, and EdgeLock™ Assurance security certification.
Technical Context
The MIMXRT1172AVM8A implements asymmetric dual-core execution: the Cortex-M7 core handles high-throughput tasks (GUI rendering, ML inference) at up to 1 GHz, while the Cortex-M4 core manages deterministic real-time control (motor PWM, sensor acquisition) at 400 MHz. Both cores access separate TCM with ECC and share 1 MB on-chip RAM with configurable ECC coverage.
It integrates a memory crypto engine enabling on-the-fly AES decryption for execute-in-place from Quad/Octal SPI or HyperFlash™, alongside hardware Elliptic Curve Cryptography (ECC), RSA-4096, SHA-2, and tamper detection - all part of the EdgeLock™ Assurance program. The device supports IEEE 1588, AVB, and TSN-capable 1 Gbps Ethernet.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Arm Cortex-M7 @ 1 GHz + Cortex-M4 @ 400 MHz: Enables concurrent high-performance compute and hard real-time control without OS-level scheduling latency. |
| Total On-Chip SRAM | 2 MB (512 KB M7 TCM + 256 KB M4 TCM + 1 MB RAM): Supports large frame buffers, neural network weights, and real-time data buffers with configurable ECC per region. |
| Security Features | Hardware AES-128/256, RSA-4096, ECC, SHA-2, TRNG, Secure JTAG, HAB v4: Meets EdgeLock™ Assurance requirements for secure boot, encrypted XIP, and runtime attestation. |
| Memory Interfaces | Quad/Octal SPI, HyperFlash™/HyperRAM™, SDRAM, NAND/NOR Flash, SD/eMMC, PSRAM, LPSDRAM: Enables flexible external memory architecture for GUI assets, firmware updates, and streaming data. |
| Connectivity | 3 × CAN-FD, 2 × USB 2.0 OTG w/ PHY, 1 × 1 Gbps ENET w/ TSN, 12 × UART, 6 × I²C, 6 × SPI: Supports industrial fieldbus integration, time-synchronized control networks, and multi-peripheral HMI subsystems. |
| Graphics & Imaging | MIPI DSI/CSI, Parallel LCD/CSI, OpenVG™ 1.1 GPU @ 500 MHz, PXP 2D accelerator: Enables 720p display rendering, camera input preprocessing, and vector graphics acceleration without CPU load. |
Pinout & Package
Package: 289-pin MAPBGA (14 mm × 14 mm, 0.8 mm pitch), RoHS-compliant, industrial temperature range (–40 °C to +105 °C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Main SoC power supply | 1.0 V ±5% supply for digital logic and CPU cores; requires low-noise regulation due to 1 GHz switching. |
| VDDA_1P0 | Analog 1.0 V domain | Independent 1.0 V supply for ADC/DAC/PLL analog circuits; must be isolated from digital noise sources. |
| BOOT_MODE0/1 | Boot configuration strapping | Hardwired pins determining boot source (e.g., QSPI flash, SD card, USB MSD); sampled at reset only. |
| ENET1_RX_DATA[3:0] | Gigabit Ethernet receive data bus | LVDS-compatible inputs supporting IEEE 802.3ab 1000BASE-T PHY interface with RGMII timing. |
| MIPI_DSI_CLK_P/N | MIPI DSI clock differential pair | High-speed differential clock (up to 2.5 Gbps) for driving MIPI DSI displays; requires controlled impedance routing. |
| WAKEUP | System wake-up interrupt input | Edge-sensitive input that exits low-power run modes (e.g., 24 MHz mode) and triggers NVIC wakeup interrupt. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric architecture | Enables separation of safety-critical real-time control (M4) from rich UI/ML workloads (M7), eliminating RTOS inter-core synchronization overhead. |
| On-the-fly AES decryption for XIP | Allows encrypted firmware images stored in external Quad/Octal SPI or HyperFlash™ to execute directly without RAM decompression - reducing attack surface and boot time. |
| Configurable ECC coverage | Per-memory-region ECC enable/disable (TCM, RAM) lets designers trade reliability for bandwidth in non-critical buffers while protecting code and control structures. |
| TSN-capable 1 Gbps Ethernet | Supports IEEE 802.1AS (time sync), 802.1Qbv (time-aware shaping), and 802.1Qci (per-stream filtering) for deterministic industrial networking. |
| MIPI DSI/CSI with integrated PHY | Eliminates need for external bridge ICs when connecting displays or image sensors - reducing BOM cost and PCB area in compact HMI designs. |
Applications
| Industrial HMI Panels | Edge AI Gateways |
|---|---|
Use Scenario: Touch-enabled factory floor operator panels with animated GUIs, real-time PLC status visualization, and local alarm logging. IC Role / Device Role / Timing Role: Primary application processor running FreeRTOS on M4 for I/O scanning and Linux/Azure RTOS on M7 for Qt-based GUI rendering and video playback. Use Value: MIPI DSI drives 720p displays directly; PXP offloads image scaling/composition; TSN Ethernet synchronizes with PLC clocks within ±1 µs jitter. | Use Scenario: Smart building gateway aggregating sensor data (vibration, temp, CO₂) and running lightweight neural networks for predictive maintenance. IC Role / Device Role / Timing Role: Dual-core inference engine: M7 executes quantized TensorFlow Lite models; M4 handles sensor fusion and CAN-FD motor telemetry collection. Use Value: 2 MB SRAM holds model weights + inference buffers; hardware AES secures OTA firmware updates; eMMC boot ensures fast, reliable recovery. |
| Motor Drive Controllers | Medical Wearables Hub |
Use Scenario: Closed-loop servo drive with field-oriented control (FOC), real-time current sensing, and web-based configuration via Ethernet. IC Role / Device Role / Timing Role: Real-time controller: M4 runs FOC loop at 20 kHz with 12 ns interrupt latency; M7 hosts web server and diagnostics UI. Use Value: 4 × FlexPWM channels generate precise gate drive signals; 2 × 12-bit ADCs sample current at 4.2 Msps; TSN ensures synchronized multi-axis motion. | Use Scenario: Multi-sensor health hub collecting ECG, SpO₂, and motion data, then transmitting processed metrics to cloud via cellular modem. IC Role / Device Role / Timing Role: Secure sensor aggregator: M4 acquires and filters analog biosignals; M7 runs BLE stack, secure TLS, and local anomaly detection. Use Value: Hardware crypto accelerates TLS handshake; tamper detection disables sensitive data on enclosure breach; 8-channel DMIC supports voice commands. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core crossover MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMXRT1176AVM8A | Includes TSN Ethernet, MIPI CSI/DSI, and tamper protection; same package and pinout. | Required for time-synchronized multi-device systems (e.g., robotics, synchronized lighting) and camera-integrated HMI. | Select when TSN, camera interface, or physical tamper resistance are mandatory - otherwise MIMXRT1172AVM8A offers identical dual-core performance at lower cost. |
| MIMXRT1175DVMAA | Commercial-grade (0–95 °C), no MIPI DSI/CSI, no TSN, but adds 10/100 ENET w/ IEEE 1588 and dual eMMC interfaces. | Suitable for cost-sensitive consumer or lab equipment where industrial temp range and advanced display/camera features are unnecessary. | Choose for commercial-temperature applications prioritizing dual eMMC storage over MIPI or TSN - not drop-in compatible due to missing MIPI pins and different thermal rating. |
Compared with MIMXRT1176AVM8A and MIMXRT1175DVMAA, the MIMXRT1172AVM8A delivers full dual-core 1 GHz/400 MHz performance and industrial temperature rating without TSN or MIPI camera support - making it optimal for display-centric HMI and edge inference where those features add cost without benefit.
Availability
MIMXRT1172AVM8A is available at Aetrix Electronics and suitable for industrial HMI panels, edge AI gateways, and motor drive controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for MIMXRT1172AVM8A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, IoT, and mobile applications.
The i.MX RT1170 family - including MIMXRT1172AVM8A - was designed to bridge the gap between application processors and microcontrollers, delivering GHz-class performance with real-time determinism and EdgeLock™-certified security for intelligent edge devices.
FAQ
What is the operating temperature range for the MIMXRT1172AVM8A?
The MIMXRT1172AVM8A is qualified for industrial temperature operation from –40 °C to +105 °C. This rating is confirmed in the official NXP i.MX RT1170 Family Fact Sheet and applies to all variants ending in "VM8A", including MIMXRT1172AVM8A. The extended range ensures reliability in factory automation, outdoor kiosks, and motor control enclosures without active cooling.
Does the MIMXRT1172AVM8A support MIPI DSI and MIPI CSI interfaces?
Yes, the MIMXRT1172AVM8A supports both MIPI DSI and MIPI CSI interfaces, as explicitly listed in the i.MX RT1170 Family Fact Sheet under device configurations. These interfaces are silicon-proven and enabled in the reference schematics for the i.MX RT1170 EVK, allowing direct connection to displays and image sensors without bridge ICs.
Is the MIMXRT1172AVM8A pin-compatible with other i.MX RT1170 family members?
The MIMXRT1172AVM8A uses the same 289-pin MAPBGA package (14 mm × 14 mm, 0.8 mm pitch) as other "VM8A" variants (e.g., MIMXRT1171AVM8A, MIMXRT1176AVM8A). Pin functions are consistent across this package variant, enabling PCB reuse where feature sets align - though unused pins (e.g., MIPI CSI on MIMXRT1171) must remain unconnected.
What security certifications apply to the MIMXRT1172AVM8A?
The MIMXRT1172AVM8A is part of NXP's EdgeLock™ Assurance program, which includes hardware-rooted secure boot (HAB v4), on-the-fly AES decryption, tamper detection, and secure key storage. Its security architecture is validated per NXP's EdgeLock™ documentation (nxp.com/EdgeLockAssurance), and it supports PSA Certified Level 3 readiness through software stack integration.
Can the MIMXRT1172AVM8A execute code directly from external HyperFlash™?
Yes, the MIMXRT1172AVM8A supports execute-in-place (XIP) from Quad/Octal SPI and HyperFlash™ devices using its integrated memory crypto engine for on-the-fly AES-128/256 decryption. This capability is documented in the i.MX RT1170 Reference Manual and enables secure, low-latency firmware execution without loading into internal RAM.
MIMXRT1172AVM8A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 289-LFBGA
- Series:
- RT1170
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M7
- Core Size:
- 32-Bit Single-Core
- Speed:
- 800MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, POR, PWM, Temp Sensor, WDT
- Number of I/O:
- 13
- Program Memory Size:
- -
- Program Memory Type:
- External Program Memory
- EEPROM Size:
- -
- RAM Size:
- 2M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.65V ~ 1.95V, 3V ~ 3.6V
- Data Converters:
- A/D 20x12b SAR; D/A 1x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MIMXRT1172AVM8A FAQ
1.How can I place an order for MIMXRT1172AVM8A through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMXRT1172AVM8A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMXRT1172AVM8A reliable?
The price and inventory of MIMXRT1172AVM8A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMXRT1172AVM8A is usually 5 days.
3.What payment methods are accepted for MIMXRT1172AVM8A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIMXRT1172AVM8A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIMXRT1172AVM8A?
MIMXRT1172AVM8A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMXRT1172AVM8A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMXRT1172AVM8A?
For technical support, including MIMXRT1172AVM8A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMXRT1172AVM8A requirements.
6.How does Aetrix verify that MIMXRT1172AVM8A is sourced from the original manufacturer or authorized distributors?
All MIMXRT1172AVM8A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMXRT1172AVM8A meets industry standards.
7.What is the process for return or replacement of MIMXRT1172AVM8A?
All MIMXRT1172AVM8A units undergo pre-shipment inspection (PSI). If there is an issue with MIMXRT1172AVM8A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMXRT1172AVM8A part is unused and in its original packaging.
Return procedure for MIMXRT1172AVM8A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MIMXRT1172AVM8A Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

