NXP Semiconductors MIMXRT1175AVM8A
- Part No.:
- MIMXRT1175AVM8A
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 289-LFBGA
- Datasheet:
-
MIMXRT1175AVM8A.pdf
- Description:
- IC MCU 32BIT EXT MEM 289MAPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
MIMXRT1175AVM8A from NXP is a dual-core Arm® Cortex®-M7 (1 GHz) + Cortex®-M4 (400 MHz) crossover MCU with 2 MB total on-chip SRAM (512 KB M7 TCM + 256 KB M4 TCM + 1 MB RAM), hardware AES-128/256 encryption, and support for Quad/Octal SPI, HyperFlash™, SDRAM, and NAND/NOR Flash - deployed in industrial HMI and edge AI inference gateways.
For engineers reviewing the MIMXRT1175AVM8A datasheet, MIMXRT1175AVM8A pinout, MIMXRT1175AVM8A application, or MIMXRT1175AVM8A equivalent, key selection criteria include real-time latency (as low as 12 ns), dual-core asymmetric execution capability, ECC-protected SRAM partitioning, secure boot via HAB, and compatibility with MCUXpresso SDK and eIQ ML toolkit.
Technical Context
The MIMXRT1175AVM8A implements a tightly coupled dual-core architecture where the Cortex-M7 core handles high-performance application tasks (e.g., GUI rendering, ML model inference) while the Cortex-M4 executes deterministic real-time control loops. It integrates a Memory Crypto Engine for on-the-fly AES decryption during XIP from Quad/Octal SPI or HyperFlash.
Security is enforced through EdgeLock™ Assurance–certified hardware: HAB v4.3, RSA-4096, ECDSA, TRNG, tamper detection, and secure JTAG/SWD. The device supports IEEE 1588, AVB, and TSN-capable Ethernet interfaces, though TSN is not enabled on this variant per family configuration table.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Arm Cortex-M7 @ 1 GHz + Cortex-M4 @ 400 MHz - enables asymmetric task partitioning between application and real-time domains |
| Total SRAM | 2 MB (512 KB M7 TCM + 256 KB M4 TCM + 1 MB RAM), all configurable with ECC - ensures data integrity in safety-critical control paths |
| Memory Interfaces | Quad/Octal SPI, HyperFlash™/HyperRAM™, SDRAM, NAND/NOR Flash, SD/eMMC, PSRAM, LPSDRAM - supports flexible boot and runtime memory expansion |
| Security Engines | HAB v4.3, AES-128/256, RSA-4096, ECDSA, TRNG, tamper detection - enables certified secure boot and encrypted firmware updates |
| Ethernet | 10/100/1000 Mbps ENET w/ IEEE 1588 & AVB - provides time-synchronized communication for industrial networking |
| Temperature Range | Commercial grade: 0 °C to 95 °C - validated for non-automotive, non-industrial ambient environments |
| Package | 289-pin MAPBGA (14 mm × 14 mm, 0.8 mm pitch) - standard footprint compatible with i.MX RT117x family PCB layouts |
Pinout & Package
289-pin Fine-Pitch Ball Grid Array (MAPBGA), 14 mm × 14 mm body, 0.8 mm ball pitch, RoHS-compliant, lead-free. Pinout defined per NXP reference schematic and i.MX RT1170 Hardware Developer's Guide (Rev. 2).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Main SOC power supply (1.0 V) | Supplies core logic; requires tight regulation and local decoupling for stable 1 GHz M7 operation |
| VDD_ARM | Cortex-M7 core voltage rail | Independent 1.0 V domain enabling dynamic voltage scaling and power gating |
| VDD_M4 | Cortex-M4 core voltage rail | Separate 1.0 V supply allows independent reset and clock gating of M4 subsystem |
| BOOT_MODE[1:0] | Boot configuration strapping pins | Determines boot source (e.g., Quad SPI, SD card, USB MSD) at power-on reset |
| ENET1_RX_DATA[3:0] | Gigabit Ethernet receive data bus | LVDS-compatible inputs supporting RGMII interface at 125 MHz for deterministic packet processing |
| QSPI_A_SCLK | Quad SPI A clock output | Drives external HyperFlash™/HyperRAM™ at up to 166 MHz DDR for XIP with AES decryption |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric execution | Enables concurrent Linux/FreeRTOS coexistence: M7 runs GUI/ML stack, M4 handles motor control or sensor fusion without OS interference |
| On-the-fly AES decryption | Allows execute-in-place (XIP) from encrypted Quad/Octal SPI flash - eliminates need for RAM-based firmware decompression |
| 2 MB ECC-configurable SRAM | Permits selective ECC enablement on critical buffers (e.g., CAN-FD message queues, safety monitor variables) without performance penalty on non-critical regions |
| Hardware crypto acceleration | Offloads TLS handshake, OTA signature verification, and secure key generation from CPU - reduces latency in cloud-connected edge devices |
| Real-time latency as low as 12 ns | Guarantees sub-microsecond interrupt response for time-critical I/O (e.g., PWM fault shutdown, encoder zero-crossing capture) |
Applications
| Industrial HMI Gateway | Edge AI Inference Node |
|---|---|
Use Scenario: Local visualization and remote command relay for PLC-controlled machinery with touchscreen UI and cloud telemetry. IC Role / Device Role / Timing Role: MIMXRT1175AVM8A serves as main application processor running LVGL-based GUI on parallel LCD while managing Modbus TCP over Gigabit Ethernet. Use Value: Dual-core isolation prevents UI freezes during real-time fieldbus polling; 2 MB SRAM hosts both framebuffer and protocol stacks without external DRAM. | Use Scenario: Battery-powered voice assistant endpoint performing keyword spotting and acoustic event detection at the edge. IC Role / Device Role / Timing Role: MIMXRT1175AVM8A executes quantized TensorFlow Lite Micro models on Cortex-M7 while Cortex-M4 handles audio preprocessing (I2S capture, noise suppression) in real time. Use Value: On-chip AES decryption enables secure firmware updates; low-power run modes at 24 MHz extend battery life between wake cycles. |
| Smart Building Controller | Medical Sensor Hub |
Use Scenario: HVAC and lighting coordination unit integrating BACnet/IP, BLE, and Zigbee via external transceivers and internal FlexIO peripherals. IC Role / Device Role / Timing Role: MIMXRT1175AVM8A acts as protocol gateway - M7 manages IP stack and web server, M4 handles time-triggered sensor polling and actuator PWM timing. Use Value: Hardware crypto engines accelerate DTLS handshakes; integrated DC-DC reduces external power components and board area. | Use Scenario: Portable ECG/PPG monitoring device aggregating analog biosensor data, applying digital filtering, and transmitting encrypted health metrics via BLE. IC Role / Device Role / Timing Role: MIMXRT1175AVM8A performs analog front-end control (12-bit ADC, DAC, comparators), real-time QRS detection, and secure BLE pairing using embedded TRNG and ECDSA. Use Value: ECC-protected SRAM stores patient identifiers and calibration coefficients; tamper detection disables sensitive functions if enclosure breach is detected. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core crossover MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMXRT1175CVM8A | Industrial temperature grade (−40 °C to +105 °C); same core speeds, memory map, and peripheral set | Suitable for factory-floor automation where ambient exceeds 95 °C | Select MIMXRT1175CVM8A when extended thermal range is required; pinout and software are identical |
| MIMXRT1176AVM8A | Adds TSN support, MIPI DSI/CSI, OpenVG 1.1, and tamper protection - otherwise identical package and pinout | Required for time-sensitive networking or embedded display pipelines | Choose MIMXRT1176AVM8A only if TSN synchronization or MIPI display interface is mandatory; otherwise MIMXRT1175AVM8A offers cost-optimal feature set |
Compared with MIMXRT1175CVM8A and MIMXRT1176AVM8A, the MIMXRT1175AVM8A delivers full dual-core performance and security features at commercial temperature range and lower BOM cost - ideal for indoor, non-harsh environment deployments where TSN or MIPI are unnecessary.
Availability
MIMXRT1175AVM8A is available at Aetrix Electronics and suitable for industrial HMI gateways, edge AI inference nodes, smart building controllers, medical sensor hubs, and voice-enabled IoT endpoints requiring stable component supply across design-in, prototyping, and production phases.
Supply support for MIMXRT1175AVM8A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The i.MX RT1170 family - including MIMXRT1175AVM8A - was designed to bridge the gap between application processors and microcontrollers, delivering GHz-class compute with real-time determinism and EdgeLock™-assured security for edge intelligence applications.
FAQ
What is the maximum operating frequency of each core in the MIMXRT1175AVM8A?
The MIMXRT1175AVM8A features an Arm Cortex-M7 core rated at 1 GHz and an Arm Cortex-M4 core rated at 400 MHz under commercial temperature conditions (0 °C to 95 °C). These frequencies are guaranteed by NXP's characterization and supported by the on-chip PLL and voltage regulation architecture. Both cores operate concurrently and independently, enabling true asymmetric multiprocessing in the MIMXRT1175AVM8A.
Does the MIMXRT1175AVM8A support Time-Sensitive Networking (TSN)?
No, the MIMXRT1175AVM8A does not support TSN. According to the official i.MX RT1170 Family Fact Sheet (IMXRT1170FAMFS REV 2), TSN capability is exclusive to the MIMXRT1176 variant. The MIMXRT1175AVM8A includes IEEE 1588 and AVB support in its 1 Gbps Ethernet controller but lacks the TSN-specific hardware timers and frame preemption logic present in the MIMXRT1176AVM8A.
What memory interfaces are supported by the MIMXRT1175AVM8A for external storage?
The MIMXRT1175AVM8A supports Quad/Octal SPI, HyperFlash™, HyperRAM™, SDRAM, NAND Flash, NOR Flash, PSRAM, LPSDRAM, SD/eMMC, and QSPI. These interfaces allow flexible boot options (e.g., XIP from HyperFlash) and runtime expansion. The Memory Crypto Engine enables AES decryption during XIP from Quad/Octal SPI or HyperFlash - a key capability confirmed in the MIMXRT1175AVM8A's security block diagram and feature list.
Is the MIMXRT1175AVM8A pin-compatible with other i.MX RT117x variants?
Yes, the MIMXRT1175AVM8A is pin-compatible with all 289-ball MAPBGA variants in the i.MX RT1170 family, including MIMXRT1171, MIMXRT1172, MIMXRT1173, MIMXRT1176, and their respective speed/temperature grades. This is explicitly stated in the family datasheet and packaging documentation. Layout reuse is possible across these parts, though thermal and power delivery must be verified per variant's specific current profile.
What development tools are officially supported for the MIMXRT1175AVM8A?
NXP officially supports the MIMXRT1175AVM8A with MCUXpresso IDE, SDK, Config Tools, and eIQ ML toolkit. The i.MX RT1170 EVK (MIMXRT1170-EVK) - based on the MIMXRT1176DVMAA - is hardware-compatible and usable for early software development, though users must account for missing TSN/MIPI features. NXP also provides reference designs, BSPs, and application notes specifically validated for the MIMXRT1175AVM8A.
MIMXRT1175AVM8A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 289-LFBGA
- Series:
- RT1170
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4, Cortex®-M7
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 400MHz, 800MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, POR, PWM, Temp Sensor, WDT
- Number of I/O:
- 13
- Program Memory Size:
- -
- Program Memory Type:
- External Program Memory
- EEPROM Size:
- -
- RAM Size:
- 2M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.65V ~ 1.95V, 3V ~ 3.6V
- Data Converters:
- A/D 20x12b SAR; D/A 1x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MIMXRT1175AVM8A FAQ
1.How can I place an order for MIMXRT1175AVM8A through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMXRT1175AVM8A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMXRT1175AVM8A reliable?
The price and inventory of MIMXRT1175AVM8A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMXRT1175AVM8A is usually 5 days.
3.What payment methods are accepted for MIMXRT1175AVM8A?
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4.How is shipping managed for MIMXRT1175AVM8A?
MIMXRT1175AVM8A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMXRT1175AVM8A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMXRT1175AVM8A?
For technical support, including MIMXRT1175AVM8A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMXRT1175AVM8A requirements.
6.How does Aetrix verify that MIMXRT1175AVM8A is sourced from the original manufacturer or authorized distributors?
All MIMXRT1175AVM8A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMXRT1175AVM8A meets industry standards.
7.What is the process for return or replacement of MIMXRT1175AVM8A?
All MIMXRT1175AVM8A units undergo pre-shipment inspection (PSI). If there is an issue with MIMXRT1175AVM8A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMXRT1175AVM8A part is unused and in its original packaging.
Return procedure for MIMXRT1175AVM8A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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