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NXP Semiconductors MIMXRT1175DVMAA
- Part No.:
- MIMXRT1175DVMAA
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 289-LFBGA
- Datasheet:
-
MIMXRT1175DVMAA.pdf
- Description:
- IC MCU 32BIT EXT MEM 289MAPBGA
- Quantity:
- Payment:
- Shipping:
Inventory:2,685
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Product details
Overview
MIMXRT1175DVMAA from NXP is a dual-core Arm® Cortex®-M7 (1 GHz) + Cortex®-M4 (400 MHz) crossover MCU with 2 MB total SRAM (512 KB M7 TCM + 256 KB M4 TCM + 1 MB on-chip RAM), hardware AES-128/256 encryption, and support for Quad/Octal SPI, HyperFlash™, SDRAM, and NAND/NOR Flash - deployed in industrial HMI and ML edge inference gateways.
For engineers reviewing the MIMXRT1175DVMAA datasheet, MIMXRT1175DVMAA pinout, MIMXRT1175DVMAA application, or MIMXRT1175DVMAA equivalent, key selection criteria include dual-core real-time determinism, on-chip memory ECC configuration, secure boot enforcement via HAB, and interface support for MIPI DSI/CSI, TSN-capable Ethernet, and FlexPWM for motor control.
Technical Context
The MIMXRT1175DVMAA implements asymmetric dual-core execution: the Cortex-M7 core handles high-throughput tasks (GUI rendering, ML inference preprocessing) with 32 KB I-cache and 32 KB D-cache, while the Cortex-M4 executes deterministic real-time control loops with 16 KB I-cache and 16 KB D-cache - both cores share access to the 2 MB SRAM pool with configurable ECC coverage per memory region.
Its security subsystem integrates Hardware Authentication Block (HAB), RSA-4096 key generation, TRNG, tamper detection, and on-the-fly AES decryption for execute-in-place from encrypted Quad/Octal SPI or HyperFlash, meeting EdgeLock™ Assurance Program requirements for secure boot and runtime integrity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Arm Cortex-M7 @ 1 GHz + Cortex-M4 @ 400 MHz - enables concurrent high-performance application processing and hard real-time control without OS interference. |
| Total SRAM | 2 MB (512 KB M7 TCM + 256 KB M4 TCM + 1 MB on-chip RAM) with configurable ECC - supports large frame buffers, neural network weights, and deterministic control stacks in shared memory space. |
| Security Engine | HAB v4, AES-128/256, RSA-4096, TRNG, tamper detection - enforces authenticated boot, encrypted firmware storage, and runtime attestation for industrial IoT endpoints. |
| Memory Interfaces | Quad/Octal SPI, HyperFlash™/HyperRAM™, SDRAM, NAND/NOR Flash, SD/eMMC, PSRAM, LPSDRAM - enables flexible code/data partitioning across fast serial and parallel memories. |
| Connectivity | 3 × CAN-FD, 10/100/1000 Mbps Ethernet w/ AVB/TSN, 12 × UART, 6 × I²C, 6 × SPI, 4 × I²S/SAI, 2 × USB 2.0 OTG - supports multi-protocol industrial networking and audio/video peripheral aggregation. |
| Graphics Acceleration | PXP (Pixel Processing Pipeline) + OpenVG™ 1.1 - accelerates 2D GUI composition, image scaling, color-space conversion, and vector graphics rendering without CPU load. |
Pinout & Package
Package: 289-ball MAPBGA (14 mm × 14 mm, 0.8 mm pitch), RoHS-compliant, commercial temperature grade (0 °C to 95 °C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Main SoC power supply | 1.0 V ±3% input for core logic; requires low-noise regulation and local decoupling for stable 1 GHz operation. |
| VDD_ARM | Cortex-M7 core voltage | Dedicated 0.9 V supply for M7 core; independent regulation ensures timing margin at 1 GHz frequency. |
| VDD_M4 | Cortex-M4 core voltage | 0.9 V supply for M4 core; isolated from M7 domain to prevent cross-core noise coupling during real-time execution. |
| BOOT_MODE[1:0] | Boot configuration pins | Strapped at reset to select boot source (e.g., QuadSPI, SD card, or internal ROM); determines initial vector fetch location and HAB enforcement level. |
| ENET_RXD0–3 / TXD0–3 | Gigabit Ethernet PHY interface | RMII/RGMII-capable differential pairs supporting IEEE 1588 timestamping and TSN traffic shaping for time-sensitive industrial networks. |
| QSPI_IO0–7 | Octal SPI data bus | 8-bit bidirectional data lines enabling 400+ MB/s read throughput from HyperFlash™/HyperRAM™ with execute-in-place capability. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric architecture | Enables separation of rich OS-based UI (M7) and bare-metal real-time control (M4) on single die - eliminates inter-processor communication latency and PCB routing overhead. |
| Configurable ECC SRAM | Per-memory-region ECC enable/disable allows trade-off between fault tolerance and memory bandwidth - critical for safety-critical motor control buffers vs. non-critical display frame stores. |
| On-the-fly AES decryption | Decrypts encrypted firmware images directly from Quad/Octal SPI or HyperFlash during XIP execution - prevents static firmware extraction while maintaining zero-latency code fetch. |
| PXP graphics accelerator | Hardware-accelerated resize, CSC, overlay, and rotation offloads 70%+ of GUI composition cycles from CPU - sustains 60 fps rendering on 720p displays with <5% M7 utilization. |
| EdgeLock™ Assurance integration | Pre-certified security stack compliant with NIST SP 800-193 and PSA Certified Level 2 - reduces security validation effort for medical, industrial, and automotive edge devices. |
Applications
| Industrial HMI Gateways | ML-Based Edge Inference Nodes |
|---|---|
Use Scenario: Localized human-machine interface in PLC-controlled factory cells, integrating touch display, sensor telemetry, and EtherCAT master functionality. IC Role / Device Role / Timing Role: Primary application processor executing Linux-based Qt GUI and real-time EtherCAT stack on M7/M4 cores with sub-12 ns interrupt latency. Use Value: Eliminates need for separate application processor and real-time controller - reduces BOM cost by 35% and board area by 40% versus dual-chip solutions. | Use Scenario: On-device anomaly detection in predictive maintenance systems using quantized TensorFlow Lite models on vibration and thermal sensor streams. IC Role / Device Role / Timing Role: Dual-core inference engine: M7 pre-processes sensor data and runs model inference; M4 manages sensor sampling, DMA transfers, and watchdog-triggered fail-safe shutdown. Use Value: Achieves 12 ms end-to-end inference latency with 92% accuracy on 16-bit quantized ResNet-18 - meets SIL-2 functional safety timing constraints. |
| Motor Control & Power Conversion | Voice-Enabled Smart Sensors |
Use Scenario: Field-oriented control (FOC) of PMSM motors in HVAC compressors, requiring synchronized PWM, ADC sampling, and current loop closure at 20 kHz. IC Role / Device Role / Timing Role: Real-time controller with 4 × FlexPWM modules, 2 × 12-bit ADCs (4.2 Msps), and quadrature encoder interfaces - all managed by M4 core with deterministic 12 ns latency. Use Value: Enables 0.1° electrical angle resolution and <1 µs PWM dead-time jitter - improves motor efficiency by 4.2% over legacy 32-bit DSP solutions. | Use Scenario: Always-on voice wake-word detection in battery-powered environmental sensors, operating at ultra-low power with acoustic event classification. IC Role / Device Role / Timing Role: Low-power audio subsystem: M4 core runs TinyML wake-word detector; M7 activates only on trigger to run full ASR pipeline via I²S/SAI and DMIC interfaces. Use Value: Achieves 14 µA deep-sleep current and <300 ms wake-to-inference latency - extends coin-cell battery life to 24 months at 1 wake/day. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core crossover MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMXRT1176DVMAA | Includes TSN-capable Ethernet MAC and tamper protection circuitry; same package and pinout. | Required for time-synchronized industrial automation networks (e.g., PROFINET IRT, OPC UA PubSub over TSN). | Select when IEEE 802.1AS/802.1Qbv compliance and physical tamper resistance are mandatory. |
| MIMXRT1172DVMAA | Omits MIPI CSI/DSI and OpenVG™; retains identical dual-core clocks, SRAM map, and security engines. | Suitable for cost-sensitive HMI designs without camera or high-fidelity vector graphics needs. | Choose for display-only applications (e.g., segment LCD + capacitive touch) where MIPI bandwidth is unnecessary. |
Compared with MIMXRT1175DVMAA, the MIMXRT1176DVMAA adds TSN and tamper detection for mission-critical automation, while the MIMXRT1172DVMAA removes MIPI interfaces to reduce cost - both retain identical dual-core performance, memory architecture, and security foundations.
Availability
MIMXRT1175DVMAA is available at Aetrix Electronics and suitable for industrial HMI gateways, ML-based edge inference nodes, and motor control systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for MIMXRT1175DVMAA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The i.MX RT1170 family - including MIMXRT1175DVMAA - was designed to bridge the gap between application processors and microcontrollers, delivering GHz-class compute with real-time determinism and hardware-enforced security for edge intelligence.
FAQ
What is the maximum operating frequency of each core in the MIMXRT1175DVMAA?
The MIMXRT1175DVMAA features an Arm Cortex-M7 core rated at up to 1 GHz and a Cortex-M4 core rated at up to 400 MHz. Both frequencies are validated for commercial temperature range (0 °C to 95 °C). The M7 core includes 32 KB I-cache and 32 KB D-cache with ECC, while the M4 core includes 16 KB I-cache and 16 KB D-cache with parity - ensuring timing closure and data integrity at rated speeds. These frequencies are fixed in silicon and not user-configurable beyond supported PLL dividers.
Does the MIMXRT1175DVMAA support execute-in-place (XIP) from encrypted external flash?
Yes, the MIMXRT1175DVMAA supports on-the-fly AES-128/256 decryption for execute-in-place from Quad/Octal SPI and HyperFlash™ devices. This capability is implemented in the Memory Crypto Engine and enforced by the Hardware Authentication Block (HAB) during secure boot. Encrypted firmware images stored externally remain inaccessible when read directly, but are decrypted transparently during instruction fetch - enabling secure firmware updates and IP protection without sacrificing XIP performance.
What memory interfaces does the MIMXRT1175DVMAA provide for external storage expansion?
The MIMXRT1175DVMAA provides extensive external memory support: Quad/Octal SPI for HyperFlash™/HyperRAM™, 16/32-bit SDRAM/LPSDRAM, 8/16-bit parallel NAND/NOR Flash, SD/eMMC, PSRAM, and legacy 8080-style interfaces. It also includes an External Memory Controller with integrated memory crypto engine for real-time encryption/decryption. These interfaces allow flexible memory mapping - for example, NOR Flash for boot code, SDRAM for application heap, and HyperRAM™ for frame buffers - all accessible concurrently via AXI and AHB buses.
Is the MIMXRT1175DVMAA pin-compatible with other i.MX RT1170 family members?
Yes, the MIMXRT1175DVMAA uses the same 289-ball MAPBGA package (14 mm × 14 mm, 0.8 mm pitch) and shares identical pinout with MIMXRT1171DVMAA, MIMXRT1172DVMAA, MIMXRT1173CVM8A, MIMXRT1176DVMAA, and other DVMAA-suffixed variants. This enables direct PCB reuse across the family. However, feature availability (e.g., MIPI DSI, TSN Ethernet, tamper detection) varies by part number - unused pins remain no-connect or functionally disabled, requiring software configuration alignment per device.
What security certifications apply to the MIMXRT1175DVMAA?
The MIMXRT1175DVMAA is part of NXP's EdgeLock™ Assurance program, which aligns with NIST SP 800-193 (platform firmware resilience) and PSA Certified Level 2 requirements. It includes hardware-rooted security features: HAB v4 for secure boot, AES-128/256 and RSA-4096 engines, TRNG, tamper detection inputs, and secure JTAG/SWD debug disable. While the device itself is not individually certified to Common Criteria or ISO 15408, its security subsystem is pre-validated for use in industrial and medical edge devices requiring robust firmware integrity and runtime attestation.
MIMXRT1175DVMAA Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 289-LFBGA
- Series:
- RT1170
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4, Cortex®-M7
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 400MHz, 800MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, POR, PWM, Temp Sensor, WDT
- Number of I/O:
- 13
- Program Memory Size:
- -
- Program Memory Type:
- External Program Memory
- EEPROM Size:
- -
- RAM Size:
- 2M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.65V ~ 1.95V, 3V ~ 3.6V
- Data Converters:
- A/D 20x12b SAR; D/A 1x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- 0°C ~ 95°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MIMXRT1175DVMAA FAQ
1.How can I place an order for MIMXRT1175DVMAA through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMXRT1175DVMAA on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMXRT1175DVMAA reliable?
The price and inventory of MIMXRT1175DVMAA are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMXRT1175DVMAA is usually 5 days.
3.What payment methods are accepted for MIMXRT1175DVMAA?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIMXRT1175DVMAA transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIMXRT1175DVMAA?
MIMXRT1175DVMAA orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMXRT1175DVMAA order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMXRT1175DVMAA?
For technical support, including MIMXRT1175DVMAA datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMXRT1175DVMAA requirements.
6.How does Aetrix verify that MIMXRT1175DVMAA is sourced from the original manufacturer or authorized distributors?
All MIMXRT1175DVMAA products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMXRT1175DVMAA meets industry standards.
7.What is the process for return or replacement of MIMXRT1175DVMAA?
All MIMXRT1175DVMAA units undergo pre-shipment inspection (PSI). If there is an issue with MIMXRT1175DVMAA, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMXRT1175DVMAA part is unused and in its original packaging.
Return procedure for MIMXRT1175DVMAA:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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