My Inquiry
My Account
NXP Semiconductors MIMXRT117CAVM8A
- Part No.:
- MIMXRT117CAVM8A
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 289-LFBGA
- Datasheet:
-
MIMXRT117CAVM8A.pdf
- Description:
- MIMXRT117CAVM8A
- Quantity:
- Payment:
- Shipping:
Inventory:2,287
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MIMXRT117CAVM8A from NXP Semiconductors is an automotive-qualified dual-core crossover processor featuring an Arm Cortex-M7 core operating at 800 MHz and a Cortex-M4 core at 400 MHz, with 2 MB on-chip SRAM (including 512 KB configurable TCM), integrated DCDC/LDO power management, and support for eMMC 5.0/SD 3.0, FlexSPI, CAN-FD, and Gigabit Ethernet with TSN - deployed in industrial HMI and automotive instrument cluster applications.
For engineers reviewing the MIMXRT117CAVM8A datasheet, MIMXRT117CAVM8A pinout, MIMXRT117CAVM8A application, or MIMXRT117CAVM8A equivalent, key selection considerations include its -40°C to +125°C automotive junction temperature rating, 289-pin MAPBGA package, dual-core asymmetric processing capability, hardware security acceleration (CAAM, HAB, OTFAD), and full feature set including three FlexCAN-FD modules, two USB 2.0 OTG controllers, and dual 1 Gb Ethernet interfaces (one with AVB, one with TSN).
Technical Context
The MIMXRT117CAVM8A implements a tightly coupled dual-core architecture where the Cortex-M7 handles high-performance real-time tasks (e.g., graphics rendering via PXP/GPU2D, motor control via FlexPWM) while the Cortex-M4 manages deterministic I/O and communication stacks (e.g., CAN-FD protocol handling, secure boot verification). Both cores share access to 2 MB on-chip SRAM with ECC support on TCM and dedicated OCRAM regions.
It integrates full automotive-grade connectivity: three FlexCAN-FD modules compliant with ISO 11898-1 and CAN 2.0B, dual 1 Gb Ethernet controllers (ENET_QOS with IEEE 802.1AS/1-Qav for TSN, ENET_1G with AVB), and two uSDHC interfaces supporting eMMC 5.0 HS400 (up to 400 MB/s) and SD 3.0 (up to 100 MB/s), all operating within the -40°C to +125°C junction temperature range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | Dual-core: Arm Cortex-M7 @ 800 MHz + Cortex-M4 @ 400 MHz - enables asymmetric real-time processing with hardware cache coherency support. |
| On-chip Memory | 2 MB SRAM total: 512 KB configurable as M7 I/D-TCM, 256 KB as M4 TCM, 1.25 MB OCRAM - eliminates need for external RAM in many HMI and control designs. |
| Temperature Grade | Automotive AEC-Q100 qualified, -40°C to +125°C junction temperature - suitable for under-hood and instrument cluster deployment without derating. |
| Connectivity | 3× FlexCAN-FD, 2× USB 2.0 OTG (with PHY), 2× uSDHC (eMMC 5.0/SD 3.0), 2× 1 Gb Ethernet (AVB + TSN), 12× UART, 6× I²C, 6× SPI - meets automotive domain controller I/O density requirements. |
| Security | HAB v4, CAAM with PKHA/RNG4/AES-128/256, OTFAD, SNVS with SRTC, PUF, and 4 KB secure RAM - enables certified secure boot and encrypted XIP from external Flash. |
| Power Management | Integrated DCDC (1.0 V / 1.8 V outputs) and LDOs - reduces external PMIC count by ≥3 regulators and simplifies power sequencing. |
| Display & Graphics | eLCDIF + LCDIFv2 (8-layer alpha blending), MIPI DSI (2-lane, 1.5 Gbps), PXP 2D accelerator, GPU2D vector engine - supports WXGA@60Hz displays with rich UI composition. |
Pinout & Package
289-pin MAPBGA package, 14 mm × 14 mm, 0.8 mm pitch - compatible with standard automotive PCB assembly processes and thermal vias for junction-to-board heat transfer.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Core logic supply | 1.0 V input for Cortex-M7/M4 cores and system logic; requires low-noise regulation per NXP AN12422. |
| VDD_ARM | M7 core supply | 1.0 V dedicated rail for Cortex-M7; decoupling must meet 100 nF + 1 µF per power domain per datasheet Section 4.2. |
| VDD_M4 | M4 core supply | 1.0 V dedicated rail for Cortex-M4; independent from VDD_ARM to enable independent core power gating. |
| BOOT_MODE[1:0] | Boot configuration | Strapped inputs determining boot source (FlexSPI, SD, NAND); must be stable before POR release per Table 5-1. |
| ENET1_RX_DATA[3:0] | Gigabit Ethernet receive | RMII/RGMII interface pins for first 1 Gb Ethernet port with AVB support; require 50 Ω controlled impedance routing. |
| CANFD1_TX / CANFD1_RX | CAN-FD channel 1 | Differential pair for first CAN-FD interface compliant with ISO 11898-1; supports data rates up to 5 Mbps. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric processing | Enables concurrent execution of safety-critical control (M4) and rich UI/audio/video (M7) without OS-level scheduling overhead. |
| Hardware crypto acceleration (CAAM) | Offloads AES-128/256, SHA-1/2, RSA-4096, and ECDSA operations from CPU - reduces secure boot time by >60% vs software-only implementation. |
| On-the-Fly AES Decryption (OTFAD) | Decrypts FlexSPI-connected external Flash in real time during XIP execution - eliminates need for RAM-based decryption buffers and preserves memory footprint. |
| Integrated DCDC + LDO power management | Reduces external regulator count by ≥3 devices and eliminates discrete power sequencing IC - lowers BOM cost and board area by ~120 mm². |
| TSN-capable Gigabit Ethernet (ENET_QOS) | Supports IEEE 802.1AS (time sync) and 802.1Qav (traffic shaping) - enables deterministic audio/video streaming in automotive ADAS domains. |
Applications
| Industrial HMI | Automotive Instrument Cluster |
|---|---|
Use Scenario: Touch-enabled dashboard with animated gauges, navigation overlays, and real-time vehicle telemetry. IC Role / Device Role / Timing Role: Primary application processor managing LCDIFv2 display composition, PXP-accelerated graphics, and CAN-FD telemetry ingestion. Use Value: Dual-core architecture isolates UI rendering (M7) from CAN message parsing (M4), ensuring <10 ms gauge update latency even under full network load. |
Use Scenario: Safety-critical digital cluster with redundant speed/tachometer rendering and ADAS warning overlays. IC Role / Device Role / Timing Role: ASIL-B capable processor executing certified motor control firmware on M4 while M7 drives MIPI DSI display with hardware alpha blending. Use Value: Integrated OTFAD and HAB enable secure boot from encrypted external Flash, meeting UNECE R155 compliance for firmware integrity. |
| Motor Control Gateway | Point-of-Sale Terminal |
Use Scenario: Multi-axis servo drive with EtherCAT fieldbus, real-time motion profiling, and local HMI. IC Role / Device Role / Timing Role: Real-time motion controller using FlexPWM (16-bit resolution, 8 channels) and GPT timers for µs-level PWM synchronization. Use Value: Hardware FlexPWM and quadrature decoder modules eliminate FPGA or external timer ICs - reducing latency to <500 ns between encoder capture and PWM update. |
Use Scenario: Secure retail terminal with EMV contactless payment, biometric authentication, and encrypted receipt printing. IC Role / Device Role / Timing Role: Secure transaction processor leveraging CAAM for EMV cryptographic operations and EMV SIM modules for smart card interface. Use Value: Dual EMV SIM interfaces and hardware RNG4 meet PCI PTS v6.0 requirements for tamper-resistant key generation and transaction signing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core crossover processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMXRT1176AVM8A | Includes GPU2D vector graphics engine and MIPI CSI camera interface not present in MIMXRT117CAVM8A. | Required for vision-based applications (e.g., driver monitoring, gesture control) needing hardware Bezier curve tessellation and 2-lane MIPI CSI. | Select when vector graphics acceleration or parallel/MIPI camera input is mandatory; otherwise MIMXRT117CAVM8A offers identical dual-core performance at lower cost. |
| MIMXRT117HAVM8A | Features 1 Gb Ethernet with AVB (not TSN) and lacks second 1 Gb Ethernet port; no ENET_QOS module. | Suitable for infotainment head units requiring AVB audio streaming but not time-synchronized sensor fusion networks. | Choose for AVB-only Ethernet needs; MIMXRT117CAVM8A provides broader networking flexibility with both AVB and TSN ports. |
Compared with MIMXRT1176AVM8A and MIMXRT117HAVM8A, the MIMXRT117CAVM8A delivers full automotive TSN+AVB dual Ethernet capability and complete FlexCAN-FD support without GPU2D or MIPI CSI - making it optimal for instrument clusters and gateways where deterministic networking and functional safety outweigh advanced vision features.
Availability
MIMXRT117CAVM8A is available at Aetrix Electronics and suitable for automotive instrument clusters, industrial HMI systems, and motor control gateways requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for MIMXRT117CAVM8A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The i.MX RT1170 family - including MIMXRT117CAVM8A - was designed as an automotive-qualified crossover processor line bridging MCU simplicity with MPU-level performance, targeting ASIL-B functional safety applications in digital cockpits and domain controllers.
FAQ
What is the maximum operating frequency of each core in the MIMXRT117CAVM8A?
The MIMXRT117CAVM8A features an Arm Cortex-M7 core rated for 800 MHz operation and an Arm Cortex-M4 core rated for 400 MHz operation. These frequencies are guaranteed across the full -40°C to +125°C automotive junction temperature range and under specified voltage conditions per the IMXRT1170AEC Rev. 5 datasheet Section 4.2. Both cores operate independently with dedicated TCM and cache resources.
Does the MIMXRT117CAVM8A support encrypted boot from external Flash memory?
Yes, the MIMXRT117CAVM8A supports encrypted boot via its On-the-Fly AES Decryption (OTFAD) module, which decrypts FlexSPI-connected external Flash during XIP execution. Combined with High Assurance Boot (HAB) and CAAM-based key management, this enables secure firmware loading without exposing decrypted code in RAM - a requirement for automotive UNECE R155 compliance.
What Ethernet capabilities does the MIMXRT117CAVM8A provide?
The MIMXRT117CAVM8A integrates two independent 1 Gb Ethernet controllers: one with Audio Video Bridging (AVB) support and one with Time-Sensitive Networking (TSN) capability (ENET_QOS compliant with IEEE 802.1AS and 802.1Qav). This dual-port configuration enables synchronized sensor fusion and deterministic audio streaming in automotive domain controllers without external switches.
How much on-chip SRAM does the MIMXRT117CAVM8A include, and how is it allocated?
The MIMXRT117CAVM8A includes 2 MB of on-chip SRAM, structured as 512 KB configurable FlexRAM (allocatable as M7 I/D-TCM or general-purpose OCRAM), 256 KB dedicated M4 TCM, and 1.25 MB fixed OCRAM. ECC is enabled on TCM regions, and the memory map is statically defined in the reference manual - no runtime reconfiguration of TCM size is supported.
Is the MIMXRT117CAVM8A qualified for automotive applications?
Yes, the MIMXRT117CAVM8A is AEC-Q100 qualified for automotive use with a junction temperature range of -40°C to +125°C. It meets automotive reliability standards including HTOL, TC, and ESD testing, and is documented in the "i.MX RT1170 Crossover Processors Data Sheet for Automotive Products" (IMXRT1170AEC Rev. 5, 01/2024), confirming its suitability for instrument clusters and body control modules.
MIMXRT117CAVM8A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 289-LFBGA
- Series:
- RT1170
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-M7
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 800MHz
- Co-Processors/DSP:
- GPU
- RAM Controllers:
- SDRAM
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- LCD, MIPI-CSI, MIPI-DSI
- Ethernet:
- 10/100Mbps (1), 1Gbps (1)
- SATA:
- -
- USB:
- USB 2.0 OTG (2)
- Voltage - I/O:
- 1.8V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- A-HAB, ARM TZ, CAAM, Cryptography, eFuse, Random Number Generator, Secure Memory, Secure RTC, System JTAG
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 289-LFBGA (14x14)
- Additional Interfaces:
- AC'97, DMA, GPIO, I2C, I2S, MMC/SD/SDIO, PDM, SAI, SDHC, SPDIF, SPI, UART
MIMXRT117CAVM8A FAQ
1.How can I place an order for MIMXRT117CAVM8A through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMXRT117CAVM8A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMXRT117CAVM8A reliable?
The price and inventory of MIMXRT117CAVM8A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMXRT117CAVM8A is usually 5 days.
3.What payment methods are accepted for MIMXRT117CAVM8A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIMXRT117CAVM8A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIMXRT117CAVM8A?
MIMXRT117CAVM8A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMXRT117CAVM8A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMXRT117CAVM8A?
For technical support, including MIMXRT117CAVM8A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMXRT117CAVM8A requirements.
6.How does Aetrix verify that MIMXRT117CAVM8A is sourced from the original manufacturer or authorized distributors?
All MIMXRT117CAVM8A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMXRT117CAVM8A meets industry standards.
7.What is the process for return or replacement of MIMXRT117CAVM8A?
All MIMXRT117CAVM8A units undergo pre-shipment inspection (PSI). If there is an issue with MIMXRT117CAVM8A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMXRT117CAVM8A part is unused and in its original packaging.
Return procedure for MIMXRT117CAVM8A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MIMXRT117CAVM8A Tags
-
AT91SAM9260B-CU-999
Microchip Technology
-
AT91SAM9G25-CU
Microchip Technology
-
ATSAMA5D27C-CU
Microchip Technology
-
AT91SAM9X35-CU
Microchip Technology
-
AT91SAM9X25-CU
Microchip Technology
-
MCIMX6Y2CVM08AB
NXP Semiconductors
.JPG)
-
AM3352BZCZ100
Texas Instruments
-
AT91SAM9260B-CU
Microchip Technology
-
AT91SAM9260B-QU
Microchip Technology
-
ATSAMA5D31A-CU
Microchip Technology
-
AT91SAM9G20B-CU-999
Microchip Technology
-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
