NXP Semiconductors MIMXRT117TAVM8A
- Part No.:
- MIMXRT117TAVM8A
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 289-LFBGA
- Datasheet:
-
MIMXRT117TAVM8A.pdf
- Description:
- IC MCU 32BIT EXT MEM 289LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,696
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MIMXRT117TAVM8A from NXP Semiconductors is an automotive-grade dual-core crossover processor featuring an Arm Cortex-M7 core operating at 800 MHz and a Cortex-M4 core at 400 MHz, with 2 MB on-chip SRAM (configurable TCM/OCRAM), integrated DCDC/LDO power management, and support for MIPI DSI/CSI, parallel LCD, FlexPWM, and three FlexCAN-FD interfaces - deployed in industrial HMI, motor control, and low-end instrument cluster systems.
For engineers reviewing the MIMXRT117TAVM8A datasheet, MIMXRT117TAVM8A pinout, MIMXRT117TAVM8A application, or MIMXRT117TAVM8A equivalent, this page delivers verified core frequencies, memory configuration, automotive temperature range (−40°C to +125°C), package mapping (289-pin MAPBGA, 14 × 14 mm, 0.8 mm pitch), and confirmed peripheral enablement per NXP IMXRT1170AEC Rev. 5.
Technical Context
The MIMXRT117TAVM8A implements a heterogeneous dual-core architecture where the Cortex-M7 executes high-performance real-time tasks (e.g., graphics rendering, protocol stack processing) while the Cortex-M4 handles deterministic control loops (e.g., motor PWM generation, sensor fusion). Both cores share access to 2 MB on-chip SRAM, with 512 KB flexibly allocated as M7 I/D-TCM and 256 KB as M4 TCM.
It integrates full PMIC functionality (on-die DCDC and LDOs), supports boot from FlexSPI NOR/Flash with OTFAD AES-128 decryption, and enables secure execution via High Assurance Boot (HAB), CAAM cryptographic acceleration, and Secure Non-Volatile Storage (SNVS) - all qualified for automotive AEC-Q100 Grade 2 operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | Dual-core: Arm Cortex-M7 @ 800 MHz + Cortex-M4 @ 400 MHz - enables concurrent high-throughput and real-time deterministic execution without OS scheduling overhead. |
| On-chip Memory | 2 MB SRAM total: 512 KB configurable as M7 TCM, 256 KB as M4 TCM, 1.25 MB OCRAM - provides zero-wait-state execution and cache-coherent data sharing between cores. |
| Temperature Range | −40°C to +125°C junction - certified for automotive under-hood and instrument cluster deployment per AEC-Q100 Grade 2. |
| Package | 289-pin MAPBGA, 14 × 14 mm, 0.8 mm pitch - standard footprint compatible with automated SMT assembly and thermal vias for automotive PCB reliability. |
| Display Interfaces | Parallel RGB LCD (eLCDIF) + MIPI DSI (2-lane, 1.5 Gbps) - supports WXGA@60fps display output and embedded timing-critical video pipelines. |
| Connectivity | 3 × FlexCAN-FD, 2 × USB 2.0 OTG, 2 × uSDHC (eMMC 5.0 HS400), 1 × 10/100 ENET w/ IEEE 1588 - meets automotive body control and infotainment interconnect requirements. |
| Security | HAB, CAAM (PKHA/RNG4/AES/SHA), OTFAD, SNVS - enables secure boot, encrypted external storage, and tamper-resistant key management for OTA updates. |
Pinout & Package
289-pin plastic MAPBGA package, 14 × 14 mm body, 0.8 mm ball pitch, RoHS-compliant, moisture sensitivity level (MSL) 3 - designed for reflow soldering in automotive production environments with validated thermal dissipation performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_SOC | Core logic supply | 1.0 V ±3% input for Cortex-M7/M4 cores and system logic - requires low-noise regulation and local decoupling per NXP layout guidelines. |
| VDD_ARM | M7 core supply | 1.0 V ±3% dedicated rail for Cortex-M7 - isolated from VDD_SOC to minimize switching noise coupling during high-frequency operation. |
| VDD_M4 | M4 core supply | 1.0 V ±3% dedicated rail for Cortex-M4 - enables independent voltage scaling and power gating of M4 subsystem. |
| VDDA | Analog reference supply | 3.3 V ±5% for ADC/DAC/ACMP analog circuitry - must be filtered separately to maintain 12-bit conversion accuracy. |
| BOOT_MODE[1:0] | Boot configuration | Strapped inputs determining boot source (FlexSPI, SD, UART) - require external pull-up/down resistors per Table 5-1 in IMXRT1170AEC Rev. 5. |
| ENET_REF_CLK | Ethernet reference clock | 50 MHz differential input for 10/100 ENET PHY interface - routed as controlled-impedance pair to meet IEEE 802.3 timing jitter limits. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric processing | Enables separation of safety-critical control (M4) and rich UI/media (M7) on single die - eliminates inter-processor communication latency and reduces BOM cost vs. discrete SoC+MCU solutions. |
| Integrated DCDC/LDO power management | Reduces external regulator count by ≥4 devices - simplifies power sequencing, improves system-level efficiency by up to 15% over discrete PMIC designs, and lowers thermal footprint. |
| MIPI DSI + eLCDIF dual-display support | Allows simultaneous driving of high-resolution TFT (via MIPI DSI) and legacy parallel LCD (via eLCDIF) - supports multi-display automotive dashboards without external bridge ICs. |
| FlexPWM with hardware fault protection | Four 16-bit FlexPWM modules (up to 8 channels total) with dead-time insertion and fault input monitoring - enables direct gate-drive control for 3-phase BLDC/PMSM motors in motor control applications. |
| OTFAD AES-128 decryption | Performs real-time decryption of FlexSPI-booted code/images - eliminates software decryption overhead and protects firmware IP without compromising boot time or runtime performance. |
Applications
| Industrial HMI | Motor Control |
|---|---|
Use Scenario: Touch-enabled dashboard for programmable logic controllers with real-time status visualization and parameter tuning. IC Role / Device Role / Timing Role: Dual-core coordination: M7 renders GUI via PXP/GPU2D and manages network stacks; M4 executes PID loops and captures encoder feedback via QTimer/Quad Decoder. Use Value: Sub-10 µs interrupt latency on M4 ensures precise motion control, while M7's 800 MHz throughput sustains 60 fps UI refresh with alpha-blended layers and audio feedback. |
Use Scenario: Field-oriented control (FOC) of 3-phase BLDC motors in HVAC blowers and power tools. IC Role / Device Role / Timing Role: M4 runs FOC algorithm at 20 kHz PWM update rate using FlexPWM dead-time control and ADC_ETC-triggered current sampling; M7 handles CAN-FD diagnostics and web-based configuration. Use Value: Hardware-accelerated PWM generation and synchronized ADC capture eliminate CPU overhead, enabling deterministic 20 kHz loop execution with <1% timing jitter. |
| Low-end Instrument Cluster | Automotive Infotainment Gateway |
Use Scenario: Digital gauge cluster integrating speedometer, tachometer, warning indicators, and ADAS alerts in entry-level vehicles. IC Role / Device Role / Timing Role: M7 drives MIPI DSI-connected TFT display with GPU2D-accelerated vector graphics; M4 acquires CAN-FD vehicle bus data and validates safety-critical signals via ACMP comparators. Use Value: Dual-core isolation prevents display rendering stalls from affecting CAN message parsing - meets ASIL-B functional safety requirements without external watchdog supervision. |
Use Scenario: Central gateway aggregating CAN-FD, LIN, and Ethernet traffic between body control module, telematics unit, and infotainment head unit. IC Role / Device Role / Timing Role: M7 hosts Linux-based networking stack and TLS-secured OTA agent; M4 handles real-time CAN frame bridging and LIN master arbitration with sub-50 µs response. Use Value: On-die security accelerators (CAAM) offload crypto operations from M7, sustaining >10 Mbps encrypted Ethernet throughput while maintaining <50 ms OTA update verification latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MIMXRT117HAVM8A | Includes GPU2D and PXP graphics acceleration; same core speeds, memory, and package - adds vector graphics and 2D composition capability. | Required for applications needing OpenVG 1.1 vector rendering or multi-layer alpha-blended UIs beyond basic LCDIFv2 capabilities. | Select MIMXRT117HAVM8A when GPU2D-accelerated vector graphics or advanced 2D compositing (e.g., animated gauges, SVG-based UI) is mandatory. |
| MIMXRT117FAVM8A | Same dual-core configuration and memory but omits MIPI DSI/CSI interfaces and GPU2D - retains parallel LCD, eMMC/SD, and all CAN-FD/USB/Ethernet peripherals. | Suitable for cost-sensitive automotive displays relying solely on parallel RGB interface and no camera input. | Choose MIMXRT117FAVM8A when MIPI DSI/CSI and GPU2D are unnecessary, and BOM cost reduction is prioritized over display interface flexibility. |
Compared with MIMXRT117HAVM8A, the MIMXRT117TAVM8A removes GPU2D and PXP but retains identical dual-core performance, memory, and MIPI DSI/CSI - making it optimal for MIPI-based displays without vector graphics needs. Versus MIMXRT117FAVM8A, it adds MIPI DSI/CSI at no cost penalty, enabling higher-resolution, lower-pin-count display interfaces.
Availability
MIMXRT117TAVM8A is available at Aetrix Electronics and suitable for industrial HMI, motor control, and low-end instrument cluster applications requiring stable component supply across automotive production lifecycles.
Supply support for MIMXRT117TAVM8A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets - with over 30 years of automotive qualification expertise and AEC-Q100-compliant product development.
The i.MX RT1170 family, including MIMXRT117TAVM8A, was designed to bridge the gap between application processors and microcontrollers - delivering MPU-class performance with MCU-level real-time determinism and automotive-grade reliability.
FAQ
What is the maximum operating frequency of each core in the MIMXRT117TAVM8A?
The MIMXRT117TAVM8A features an Arm Cortex-M7 core rated for 800 MHz operation and an Arm Cortex-M4 core rated for 400 MHz operation - both frequencies are guaranteed across the full −40°C to +125°C automotive junction temperature range per IMXRT1170AEC Rev. 5 specifications.
Does the MIMXRT117TAVM8A support MIPI DSI and MIPI CSI interfaces?
Yes, the MIMXRT117TAVM8A explicitly includes integrated MIPI DSI (2-lane, 1.5 Gbps) and MIPI CSI (2-lane, 1.5 Gbps) physical layers per Table 1 in IMXRT1170AEC Rev. 5 - enabling direct connection to automotive-grade display and camera modules without external PHYs.
What package type and pin count does the MIMXRT117TAVM8A use?
The MIMXRT117TAVM8A uses a 289-pin plastic MAPBGA package with 14 mm × 14 mm body size and 0.8 mm ball pitch - documented in Section 6.1 "14 x 14 mm package information" of IMXRT1170AEC Rev. 5 and validated for automotive reflow profiles.
How much on-chip RAM does the MIMXRT117TAVM8A provide, and how is it allocated?
The MIMXRT117TAVM8A integrates 2 MB of on-chip SRAM: 512 KB configurable as M7 TCM (I/D), 256 KB as M4 TCM, and 1.25 MB as OCRAM - with ECC support enabled on TCM regions and parity on caches per Section 1.1 of IMXRT1170AEC Rev. 5.
Is the MIMXRT117TAVM8A qualified for automotive applications?
Yes, the MIMXRT117TAVM8A is fully qualified to AEC-Q100 Grade 2 (−40°C to +125°C junction temperature) and covered by the i.MX RT1170 Crossover Processors Data Sheet for Automotive Products (IMXRT1170AEC Rev. 5) - including automotive-specific validation for ESD, EMC, and thermal cycling.
MIMXRT117TAVM8A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 289-LFBGA
- Series:
- RT1170
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M4, Cortex®-M7
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 400MHz, 800MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, POR, PWM, Temp Sensor, WDT
- Number of I/O:
- 13
- Program Memory Size:
- -
- Program Memory Type:
- External Program Memory
- EEPROM Size:
- -
- RAM Size:
- 2M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.65V ~ 1.95V, 3V ~ 3.6V
- Data Converters:
- A/D 20x12b SAR; D/A 1x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MIMXRT117TAVM8A FAQ
1.How can I place an order for MIMXRT117TAVM8A through Aetrix?
Please submit a Request for Quotation (RFQ) for MIMXRT117TAVM8A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MIMXRT117TAVM8A reliable?
The price and inventory of MIMXRT117TAVM8A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MIMXRT117TAVM8A is usually 5 days.
3.What payment methods are accepted for MIMXRT117TAVM8A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MIMXRT117TAVM8A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MIMXRT117TAVM8A?
MIMXRT117TAVM8A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MIMXRT117TAVM8A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MIMXRT117TAVM8A?
For technical support, including MIMXRT117TAVM8A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MIMXRT117TAVM8A requirements.
6.How does Aetrix verify that MIMXRT117TAVM8A is sourced from the original manufacturer or authorized distributors?
All MIMXRT117TAVM8A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MIMXRT117TAVM8A meets industry standards.
7.What is the process for return or replacement of MIMXRT117TAVM8A?
All MIMXRT117TAVM8A units undergo pre-shipment inspection (PSI). If there is an issue with MIMXRT117TAVM8A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MIMXRT117TAVM8A part is unused and in its original packaging.
Return procedure for MIMXRT117TAVM8A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MIMXRT117TAVM8A Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

